9d45f1936c
git-svn-id: https://svn.disconnected-by-peer.at/svn/linamh/trunk/linamh@713 6952d904-891a-0410-993b-d76249ca496b
121 lines
4.5 KiB
Diff
121 lines
4.5 KiB
Diff
# Send to upstream BOCHS
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This ACPI BIOS patch provides:
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- The PCI bus definition for PIC, HPET, RTC, SMC and OSYS and SMIF
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- An PBLK which provides the size of the L2 and L3 caches
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- If newer hardware like ICH6 IDE is found, init it
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Signed-off-by: Alex Graf - http://alex.csgraf.de
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Index: kvm-77/bios-mac/acpi-dsdt.dsl
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===================================================================
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--- kvm-77.orig/bios-mac/acpi-dsdt.dsl
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+++ kvm-77/bios-mac/acpi-dsdt.dsl
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@@ -78,6 +78,47 @@ DefinitionBlock (
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/* PCI Bus definition */
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Scope(\_SB) {
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+ Device (HPET)
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+ {
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+ Name (_HID, EisaId ("PNP0103"))
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+ Name (_CID, 0x010CD041)
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+ Name (BUF0, ResourceTemplate ()
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+ {
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+ IRQNoFlags ()
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+ {2}
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+ IRQNoFlags ()
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+ {8}
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+ Memory32Fixed (ReadOnly,
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+ 0xFED00000, // Address Base
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+ 0x00000400, // Address Length
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+ _Y16)
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+ })
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+ Method (_STA, 0, NotSerialized)
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+ {
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+ Return (0x0F)
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+ }
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+ Method (_CRS, 0, Serialized)
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+ {
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+ Return (BUF0)
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+ }
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+ }
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+ Device (SMC)
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+ {
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+ Name (_HID, EisaId ("APP0001"))
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+ Name (_CID, "smc-napa")
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+ Name (_STA, 0x0B)
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+ Name (_CRS, ResourceTemplate ()
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+ {
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+ IO (Decode16,
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+ 0x0300, // Range Minimum
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+ 0x0300, // Range Maximum
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+ 0x01, // Alignment
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+ 0x20, // Length
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+ )
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+ IRQNoFlags ()
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+ {6}
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+ })
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+ }
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Device(PCI0) {
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00)
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Index: kvm-77/bios-mac/rombios32.c
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===================================================================
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--- kvm-77.orig/bios-mac/rombios32.c
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+++ kvm-77/bios-mac/rombios32.c
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@@ -628,6 +628,9 @@ void smp_probe(void)
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#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
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#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
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#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
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+#define PCI_DEVICE_ID_INTEL_874079 0x27a0 /* i945GM Express Chipset */
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+#define PCI_DEVICE_ID_INTEL_945GL 0x27b9 /* ICH7 LPC */
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+#define PCI_DEVICE_ID_INTEL_ICH6IDE 0x269e
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#define PCI_VENDOR_ID_IBM 0x1014
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#define PCI_VENDOR_ID_APPLE 0x106b
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@@ -641,7 +644,9 @@ static uint32_t pci_bios_io_addr;
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static uint32_t pci_bios_mem_addr;
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static uint32_t pci_bios_bigmem_addr;
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/* host irqs corresponding to PCI irqs A-D */
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-static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
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+static uint8_t pci_irqs[4] = { 11, 10, 11, 10 };
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+//static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
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+//static uint8_t pci_irqs[4] = { 0x10, 0x11, 0x12, 0x13 };
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static PCIDevice i440_pcidev;
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static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
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@@ -772,7 +777,9 @@ static void pci_bios_init_bridges(PCIDev
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if (vendor_id == PCI_VENDOR_ID_INTEL &&
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(device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
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- device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
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+ device_id == PCI_DEVICE_ID_INTEL_82371AB_0 ||
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+ device_id == PCI_DEVICE_ID_INTEL_874079 ||
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+ device_id == PCI_DEVICE_ID_INTEL_945GL)) {
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int i, irq;
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uint8_t elcr[2];
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@@ -854,8 +861,9 @@ static void pci_bios_init_device(PCIDevi
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case 0x0101:
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if (vendor_id == PCI_VENDOR_ID_INTEL &&
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(device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
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- device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
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- /* PIIX3/PIIX4 IDE */
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+ device_id == PCI_DEVICE_ID_INTEL_82371AB ||
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+ device_id == PCI_DEVICE_ID_INTEL_ICH6IDE)) {
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+ /* PIIX3/PIIX4/ICH6 IDE */
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pci_config_writew(d, 0x40, 0x8000); // enable IDE0
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pci_config_writew(d, 0x42, 0x8000); // enable IDE1
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goto default_map;
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@@ -1559,6 +1567,13 @@ void acpi_bios_init(void)
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acpi_build_table_header((struct acpi_table_header *)madt,
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"APIC", madt_size, 1);
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}
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+ /* PBLK (CPU information structure) */
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+ {
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+ uint32_t *pblk = (void*) (0x410);
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+ *pblk = 0;
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+ ((char*)pblk)[4] = 64; /* size of the Level 2 cache */
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+ ((char*)pblk)[5] = 0; /* size of the Level 3 cache */
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+ }
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}
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/* SMBIOS entry point -- must be written to a 16-bit aligned address
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