# Send to upstream BOCHS
This ACPI BIOS patch provides:
- The PCI bus definition for PIC, HPET, RTC, SMC and OSYS and SMIF
- An PBLK which provides the size of the L2 and L3 caches
- If newer hardware like ICH6 IDE is found, init it
Signed-off-by: Alex Graf - http://alex.csgraf.de
Index: kvm-77/bios-mac/acpi-dsdt.dsl
===================================================================
--- kvm-77.orig/bios-mac/acpi-dsdt.dsl
+++ kvm-77/bios-mac/acpi-dsdt.dsl
@@ -78,6 +78,47 @@ DefinitionBlock (
 
     /* PCI Bus definition */
     Scope(\_SB) {
+        Device (HPET)
+        {
+            Name (_HID, EisaId ("PNP0103"))
+            Name (_CID, 0x010CD041)
+            Name (BUF0, ResourceTemplate ()
+            {
+                IRQNoFlags ()
+                    {2}
+                IRQNoFlags ()
+                    {8}
+                Memory32Fixed (ReadOnly,
+                    0xFED00000,         // Address Base
+                    0x00000400,         // Address Length
+                    _Y16)
+            })
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (0x0F)
+            }
+            Method (_CRS, 0, Serialized)
+            {
+                Return (BUF0)
+            }
+        }
+        Device (SMC)
+        {
+            Name (_HID, EisaId ("APP0001"))
+            Name (_CID, "smc-napa")
+            Name (_STA, 0x0B)
+            Name (_CRS, ResourceTemplate ()
+            {
+                IO (Decode16,
+                    0x0300,             // Range Minimum
+                    0x0300,             // Range Maximum
+                    0x01,               // Alignment
+                    0x20,               // Length
+                    )
+                IRQNoFlags ()
+                    {6}
+            })
+        }
         Device(PCI0) {
             Name (_HID, EisaId ("PNP0A03"))
             Name (_ADR, 0x00)
Index: kvm-77/bios-mac/rombios32.c
===================================================================
--- kvm-77.orig/bios-mac/rombios32.c
+++ kvm-77/bios-mac/rombios32.c
@@ -628,6 +628,9 @@ void smp_probe(void)
 #define PCI_DEVICE_ID_INTEL_82371AB_0   0x7110
 #define PCI_DEVICE_ID_INTEL_82371AB     0x7111
 #define PCI_DEVICE_ID_INTEL_82371AB_3   0x7113
+#define PCI_DEVICE_ID_INTEL_874079      0x27a0 /* i945GM Express Chipset */
+#define PCI_DEVICE_ID_INTEL_945GL       0x27b9 /* ICH7 LPC */
+#define PCI_DEVICE_ID_INTEL_ICH6IDE     0x269e
 
 #define PCI_VENDOR_ID_IBM               0x1014
 #define PCI_VENDOR_ID_APPLE             0x106b
@@ -641,7 +644,9 @@ static uint32_t pci_bios_io_addr;
 static uint32_t pci_bios_mem_addr;
 static uint32_t pci_bios_bigmem_addr;
 /* host irqs corresponding to PCI irqs A-D */
-static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
+static uint8_t pci_irqs[4] = { 11, 10, 11, 10 };
+//static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
+//static uint8_t pci_irqs[4] = { 0x10, 0x11, 0x12, 0x13 };
 static PCIDevice i440_pcidev;
 
 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
@@ -772,7 +777,9 @@ static void pci_bios_init_bridges(PCIDev
 
     if (vendor_id == PCI_VENDOR_ID_INTEL &&
        (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
-        device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
+        device_id == PCI_DEVICE_ID_INTEL_82371AB_0 ||
+        device_id == PCI_DEVICE_ID_INTEL_874079 ||
+        device_id == PCI_DEVICE_ID_INTEL_945GL)) {
         int i, irq;
         uint8_t elcr[2];
 
@@ -854,8 +861,9 @@ static void pci_bios_init_device(PCIDevi
     case 0x0101:
         if (vendor_id == PCI_VENDOR_ID_INTEL &&
            (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
-            device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
-            /* PIIX3/PIIX4 IDE */
+            device_id == PCI_DEVICE_ID_INTEL_82371AB ||
+            device_id == PCI_DEVICE_ID_INTEL_ICH6IDE)) {
+            /* PIIX3/PIIX4/ICH6 IDE */
             pci_config_writew(d, 0x40, 0x8000); // enable IDE0
             pci_config_writew(d, 0x42, 0x8000); // enable IDE1
             goto default_map;
@@ -1559,6 +1567,13 @@ void acpi_bios_init(void)
         acpi_build_table_header((struct acpi_table_header *)madt,
                                 "APIC", madt_size, 1);
     }
+    /* PBLK (CPU information structure) */
+    {
+       uint32_t *pblk = (void*) (0x410);
+       *pblk = 0;
+       ((char*)pblk)[4] = 64; /* size of the Level 2 cache */
+       ((char*)pblk)[5] = 0;  /* size of the Level 3 cache */
+    }
 }
 
 /* SMBIOS entry point -- must be written to a 16-bit aligned address