144 lines
3.5 KiB
C
144 lines
3.5 KiB
C
/*
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* BK Id: SCCS/s.atomic.h 1.8 05/17/01 18:14:24 cort
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*/
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/*
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* PowerPC atomic operations
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*/
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#ifndef _ASM_PPC_ATOMIC_H_
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#define _ASM_PPC_ATOMIC_H_
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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*
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* We can use the eieio instruction for wmb, but since it doesn't
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* give any ordering guarantees about loads, we have to use the
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* stronger but slower sync instruction for mb and rmb.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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typedef struct { volatile int counter; } ncpt_atomic_t;
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#define NCPT_ATOMIC_INIT(i) { (i) }
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#define ncpt_atomic_read(v) ((v)->counter)
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#define ncpt_atomic_set(v,i) (((v)->counter) = (i))
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extern void ncpt_atomic_clear_mask(unsigned long mask, unsigned long *addr);
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extern void ncpt_atomic_set_mask(unsigned long mask, unsigned long *addr);
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static __inline__ int ncpt_atomic_add_return(int a, ncpt_atomic_t *v)
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{
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int t;
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__asm__ __volatile__("\n\
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1: lwarx %0,0,%3\n\
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add %0,%2,%0\n\
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stwcx. %0,0,%3\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (v), "m" (v->counter)
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: "cc");
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return t;
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}
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static __inline__ int ncpt_atomic_sub_return(int a, ncpt_atomic_t *v)
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{
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int t;
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__asm__ __volatile__("\n\
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1: lwarx %0,0,%3\n\
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subf %0,%2,%0\n\
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stwcx. %0,0,%3\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (a), "r" (v), "m" (v->counter)
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: "cc");
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return t;
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}
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static __inline__ int ncpt_atomic_inc_return(ncpt_atomic_t *v)
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{
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int t;
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__asm__ __volatile__("\n\
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1: lwarx %0,0,%2\n\
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addic %0,%0,1\n\
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stwcx. %0,0,%2\n\
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bne- 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (v), "m" (v->counter)
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: "cc");
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return t;
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}
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static __inline__ int ncpt_atomic_dec_return(ncpt_atomic_t *v)
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{
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int t;
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__asm__ __volatile__("\n\
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1: lwarx %0,0,%2\n\
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addic %0,%0,-1\n\
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stwcx. %0,0,%2\n\
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bne 1b"
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: "=&r" (t), "=m" (v->counter)
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: "r" (v), "m" (v->counter)
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: "cc");
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return t;
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}
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#define ncpt_atomic_add(a, v) ((void) ncpt_atomic_add_return((a), (v)))
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#define ncpt_atomic_sub(a, v) ((void) ncpt_atomic_sub_return((a), (v)))
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#define ncpt_atomic_sub_and_test(a, v) (ncpt_atomic_sub_return((a), (v)) == 0)
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#define ncpt_atomic_inc(v) ((void) ncpt_atomic_inc_return((v)))
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#define ncpt_atomic_dec(v) ((void) ncpt_atomic_dec_return((v)))
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#define ncpt_atomic_dec_and_test(v) (ncpt_atomic_dec_return((v)) == 0)
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/*
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* Atomically test *v and decrement if it is greater than 0.
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* The function returns the old value of *v minus 1.
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*/
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static __inline__ int ncpt_atomic_dec_if_positive(ncpt_atomic_t *v)
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{
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int t;
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__asm__ __volatile__("\n"
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"1: lwarx %0,0,%2\n"
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" addic. %0,%0,-1\n"
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" blt 2f\n"
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" stwcx. %0,0,%2\n"
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" bne 1b\n"
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"2:"
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: "=&r" (t), "=m" (v->counter)
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: "r" (&v->counter), "m" (v->counter)
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: "cc");
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return t;
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}
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#define smp_mb__before_ncpt_atomic_dec() smp_mb()
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#define smp_mb__after_ncpt_atomic_dec() smp_mb()
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#define smp_mb__before_ncpt_atomic_inc() smp_mb()
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#define smp_mb__after_ncpt_atomic_inc() smp_mb()
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#endif /* _ASM_PPC_ATOMIC_H_ */
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