273 lines
6.8 KiB
C
273 lines
6.8 KiB
C
#include "sl_chacha20poly1305ietf_config.h"
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#if defined USE_SL_CHACHA20_POLY1305_IETF || defined USE_SL_SODIUM
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# include "osdep_stddef.h"
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# include "osdep_stdint.h"
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# include "osdep_stdlib.h"
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# include "osdep_stdbool.h"
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# include "private/common.h"
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# include "runtime.h"
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# include "pscompilerdep.h"
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typedef struct CPUFeatures_ {
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int initialized;
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int has_neon;
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int has_sse2;
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int has_sse3;
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int has_ssse3;
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int has_sse41;
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int has_avx;
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int has_avx2;
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int has_pclmul;
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int has_aesni;
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} CPUFeatures;
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static CPUFeatures _cpu_features;
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# define CPUID_EBX_AVX2 0x00000020
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# define CPUID_ECX_SSE3 0x00000001
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# define CPUID_ECX_PCLMUL 0x00000002
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# define CPUID_ECX_SSSE3 0x00000200
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# define CPUID_ECX_SSE41 0x00080000
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# define CPUID_ECX_AESNI 0x02000000
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# define CPUID_ECX_XSAVE 0x04000000
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# define CPUID_ECX_OSXSAVE 0x08000000
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# define CPUID_ECX_AVX 0x10000000
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# define CPUID_EDX_SSE2 0x04000000
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# define XCR0_SSE 0x00000002
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# define XCR0_AVX 0x00000004
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static int
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SLSodium_runtime_arm_cpu_features(CPUFeatures * const cpu_features)
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{
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# if !defined(__arm__) && !defined(__aarch64__) && !defined(__aarch32__)
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cpu_features->has_neon = 0;
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return -1;
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#else /* some ARM platform. */
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# define NO_INTEL /* This architecture is definitely not x86/x86-64.
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No need to probe for Intel CPU features. */
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/* Customization for Rambus Inc.FIPS Toolkit: */
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/* Use sl_cpu.c for ARM feature detection, instead of
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the default sodium code. */
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extern bool SL_ArmDetectionDone;
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extern bool SL_hasNEON;
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void SL_DetectArmFeatures(void);
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if (!SL_ArmDetectionDone)
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{
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if (!getenv("SAFEZONE_DISABLE_HW"))
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{
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SL_DetectArmFeatures();
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}
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else
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{
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SL_ArmDetectionDone = 1;
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}
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}
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cpu_features->has_neon = SL_hasNEON;
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return 0;
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# endif /* ARM variant (including ARMv7 or ARMv8). */
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}
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#ifndef NO_INTEL
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static void
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_cpuid(unsigned int cpu_info[4U], const unsigned int cpu_info_type)
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{
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# if defined(_MSC_VER) && \
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(defined(_M_X64) || defined(_M_AMD64) || defined(_M_IX86))
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__cpuid((int *) cpu_info, cpu_info_type);
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# elif defined(HAVE_CPUID)
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cpu_info[0] = cpu_info[1] = cpu_info[2] = cpu_info[3] = 0;
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# ifdef __i386__
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__asm__ __volatile__(
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"pushfl; pushfl; "
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"popl %0; "
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"movl %0, %1; xorl %2, %0; "
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"pushl %0; "
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"popfl; pushfl; popl %0; popfl"
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: "=&r"(cpu_info[0]), "=&r"(cpu_info[1])
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: "i"(0x200000));
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if (((cpu_info[0] ^ cpu_info[1]) & 0x200000) == 0x0) {
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return; /* LCOV_EXCL_LINE */
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}
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# endif
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# ifdef __i386__
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__asm__ __volatile__("xchgl %%ebx, %k1; cpuid; xchgl %%ebx, %k1"
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: "=a"(cpu_info[0]), "=&r"(cpu_info[1]),
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"=c"(cpu_info[2]), "=d"(cpu_info[3])
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: "0"(cpu_info_type), "2"(0U));
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# elif defined(__x86_64__)
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__asm__ __volatile__("xchgq %%rbx, %q1; cpuid; xchgq %%rbx, %q1"
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: "=a"(cpu_info[0]), "=&r"(cpu_info[1]),
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"=c"(cpu_info[2]), "=d"(cpu_info[3])
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: "0"(cpu_info_type), "2"(0U));
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# else
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__asm__ __volatile__("cpuid"
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: "=a"(cpu_info[0]), "=b"(cpu_info[1]),
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"=c"(cpu_info[2]), "=d"(cpu_info[3])
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: "0"(cpu_info_type), "2"(0U));
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# endif
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# else
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(void) cpu_info_type;
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cpu_info[0] = cpu_info[1] = cpu_info[2] = cpu_info[3] = 0;
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# endif
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}
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#endif
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static int
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SLSodium_runtime_intel_cpu_features(CPUFeatures * const cpu_features)
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{
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#ifndef NO_INTEL
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unsigned int cpu_info[4];
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unsigned int id;
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_cpuid(cpu_info, 0x0);
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if ((id = cpu_info[0]) == 0U) {
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return -1; /* LCOV_EXCL_LINE */
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}
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_cpuid(cpu_info, 0x00000001);
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# ifdef HAVE_EMMINTRIN_H
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cpu_features->has_sse2 = ((cpu_info[3] & CPUID_EDX_SSE2) != 0x0);
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# else
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cpu_features->has_sse2 = 0;
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# endif
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# ifdef HAVE_PMMINTRIN_H
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cpu_features->has_sse3 = ((cpu_info[2] & CPUID_ECX_SSE3) != 0x0);
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# else
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cpu_features->has_sse3 = 0;
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# endif
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# ifdef HAVE_TMMINTRIN_H
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cpu_features->has_ssse3 = ((cpu_info[2] & CPUID_ECX_SSSE3) != 0x0);
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# else
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cpu_features->has_ssse3 = 0;
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# endif
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# ifdef HAVE_SMMINTRIN_H
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cpu_features->has_sse41 = ((cpu_info[2] & CPUID_ECX_SSE41) != 0x0);
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# else
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cpu_features->has_sse41 = 0;
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# endif
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cpu_features->has_avx = 0;
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# ifdef HAVE_AVXINTRIN_H
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if ((cpu_info[2] & (CPUID_ECX_AVX | CPUID_ECX_XSAVE | CPUID_ECX_OSXSAVE)) ==
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(CPUID_ECX_AVX | CPUID_ECX_XSAVE | CPUID_ECX_OSXSAVE)) {
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uint32_t xcr0 = 0U;
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# if defined(HAVE__XGETBV) || \
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(defined(_MSC_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) && _MSC_FULL_VER >= 160040219)
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xcr0 = (uint32_t) _xgetbv(0);
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# elif defined(_MSC_VER) && defined(_M_IX86)
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__asm {
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xor ecx, ecx
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_asm _emit 0x0f _asm _emit 0x01 _asm _emit 0xd0
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mov xcr0, eax
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}
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# elif defined(HAVE_AVX_ASM)
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__asm__ __volatile__(".byte 0x0f, 0x01, 0xd0" /* XGETBV */
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: "=a"(xcr0)
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: "c"((uint32_t) 0U)
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: "%edx");
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# endif
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if ((xcr0 & (XCR0_SSE | XCR0_AVX)) == (XCR0_SSE | XCR0_AVX)) {
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cpu_features->has_avx = 1;
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}
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}
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# endif
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cpu_features->has_avx2 = 0;
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# ifdef HAVE_AVX2INTRIN_H
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if (cpu_features->has_avx) {
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unsigned int cpu_info7[4];
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_cpuid(cpu_info7, 0x00000007);
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cpu_features->has_avx2 = ((cpu_info7[1] & CPUID_EBX_AVX2) != 0x0);
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}
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# endif
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# ifdef HAVE_WMMINTRIN_H
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cpu_features->has_pclmul = ((cpu_info[2] & CPUID_ECX_PCLMUL) != 0x0);
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cpu_features->has_aesni = ((cpu_info[2] & CPUID_ECX_AESNI) != 0x0);
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# else
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cpu_features->has_pclmul = 0;
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cpu_features->has_aesni = 0;
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# endif
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return 0;
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#else
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return -1; /* Unable to probe for Intel CPU features. */
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#endif
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}
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int
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SLSodium_runtime_get_cpu_features(void)
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{
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int ret = -1;
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ret &= SLSodium_runtime_arm_cpu_features(&_cpu_features);
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ret &= SLSodium_runtime_intel_cpu_features(&_cpu_features);
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_cpu_features.initialized = 1;
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return ret;
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}
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int
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SLSodium_runtime_has_neon(void)
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{
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return _cpu_features.has_neon;
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}
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int
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SLSodium_runtime_has_sse2(void)
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{
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return _cpu_features.has_sse2;
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}
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int
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SLSodium_runtime_has_sse3(void)
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{
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return _cpu_features.has_sse3;
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}
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int
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SLSodium_runtime_has_ssse3(void)
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{
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return _cpu_features.has_ssse3;
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}
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int
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SLSodium_runtime_has_sse41(void)
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{
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return _cpu_features.has_sse41;
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}
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int
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SLSodium_runtime_has_avx(void)
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{
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return _cpu_features.has_avx;
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}
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int
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SLSodium_runtime_has_avx2(void)
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{
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return _cpu_features.has_avx2;
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}
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int
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SLSodium_runtime_has_pclmul(void)
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{
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return _cpu_features.has_pclmul;
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}
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int
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SLSodium_runtime_has_aesni(void)
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{
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return _cpu_features.has_aesni;
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}
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#endif /* USE_SL_CHACHA20_POLY1305_IETF || USE_SL_SODIUM */
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