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Mario Fetka
2017-04-22 12:53:48 +02:00
parent 0c8af0ce51
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/***************************************************************************
* *
* Copyright 2003 LSI Logic Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Logic. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Logic Corporation. *
* *
***************************************************************************
*
* Name: ATA.H
* Title: ATA and SATA Device structures and definitions
* Programmer: ----------------
* Creation Date: February 26, 2002
*
* Version History
* ---------------
*
* Last Updated
* -------------
* Version %version: 24 %
* Date Updated %date_modified: %
* Programmer %created_by: mfry %
*
* Date Who Description
* -------- --- -------------------------------------------------------
* 02/26/02 GWK Initial version
* 01/24/03 GWK Updated for SAS 1064
* 08/20/08 KAM updated for SDM big endian platform and gcc bitfields
*
*
* Description
* ------------
* This include file contains generic ATA and SATA structures and definitions.
*
*-------------------------------------------------------------------------
*/
/* If this header file has not been included yet */
#ifndef ATA_H_SOURCE
#define ATA_H_SOURCE
/* Status Register Bit Definitions */
#define ATA_STATUS_ERR (0x01)
#define ATA_STATUS_DRQ (0x08)
#define ATA_STATUS_CMD_DEP (0x10)
#define ATA_STATUS_DF (0x20)
#define ATA_STATUS_DRDY (0x40)
#define ATA_STATUS_BSY (0x80)
#define ATA_STATUS_ERR_DF (ATA_STATUS_ERR | ATA_STATUS_DF)
/* Atapi Status Register Bit Definitions */
#define ATAPI_STATUS_CHK (0x01)
#define ATAPI_STATUS_DRQ (0x08)
#define ATAPI_STATUS_SERV (0x10)
#define ATAPI_STATUS_DMRD (0x20)
#define ATAPI_STATUS_DRDY (0x40)
#define ATAPI_STATUS_BSY (0x80)
/* Atapi Interrupt Reason Register Bit Definitions */
#define ATAPI_INTERRUPT_REASON_CD (0x01)
#define ATAPI_INTERRUPT_REASON_IO (0x02)
#define ATAPI_INTERRUPT_REASON_REL (0x04)
#define ATAPI_INTERRUPT_REASON_TAG_SHIFT (3)
#define ATAPI_INTERRUPT_REASON_TAG_MASK (0xF8)
/* Error Register Bit Definitions */
#define ATA_ERR_ICRC (0x80) /* ultra DMA CRC */
#define ATA_ERR_UNC (0x40) /* uncorrectable error */
#define ATA_ERR_WP (0x40) /* write-protect bit */
#define ATA_ERR_MC (0x20) /* media changed */
#define ATA_ERR_IDNF (0x10) /* id not found */
#define ATA_ERR_MCR (0x08) /* media change requested */
#define ATA_ERR_ABRT (0x04) /* aborted command */
#define ATA_ERR_NM (0x02) /* no media present */
/* Atapi Error Register Bit Definitions */
#define ATAPI_ERR_ILI (0x01)
#define ATAPI_ERR_EOM (0x02)
#define ATAPI_ERR_ABRT (0x04)
#define ATAPI_ERR_SENSE_KEY_SHIFT (3)
#define ATAPI_ERR_SENSE_KEY_TAG_MASK (0xF8)
/* Device & Device/Head Register Bit Definitions */
#define ATA_DEVICE_LBA (0x40)
/* Device Control Register Bit Definitions */
#define ATA_DEVICE_CONTROL_SRST (0x04)
#define ATA_DEVICE_CONTROL_NIEN (0x02)
/*
* define the ATA command set
*/
#define ATA_CMD_CHECK_POWER_MODE 0xE5
#define ATA_CMD_DEVICE_CONFIGURATION 0xB1
#define ATA_CMD_DOWNLOAD_MICROCODE 0x92
#define ATA_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90
#define ATA_CMD_FLUSH_CACHE 0xE7
#define ATA_CMD_FLUSH_CACHE_EXT 0xEA
#define ATA_CMD_GET_MEDIA_STATUS 0xDA
#define ATA_CMD_IDENTIFY_DEVICE 0xEC
#define ATA_CMD_IDENTIFY_PACKET_DEVICE 0xA1
#define ATA_CMD_IDLE 0xE3
#define ATA_CMD_IDLE_IMMEDIATE 0xE1
#define ATA_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91
#define ATA_CMD_MEDIA_EJECT 0xED
#define ATA_CMD_MEDIA_LOCK 0xDE
#define ATA_CMD_MEDIA_UNLOCK 0xDF
#define ATA_CMD_NATIVE_MAX_ADDRESS 0xF8
#define ATA_CMD_NATIVE_MAX_ADDRESS_EXT 0x27
#define ATA_CMD_NOP 0x00
#define ATA_CMD_PACKET 0xA0
#define ATA_CMD_READ_BUFFER 0xE4
#define ATA_CMD_READ_DMA 0xC8
#define ATA_CMD_READ_DMA_EXT 0x25
#define ATA_CMD_READ_DMA_QUEUED 0xC7
#define ATA_CMD_READ_DMA_QUEUED_EXT 0x26
#define ATA_CMD_READ_FPDMA_QUEUED 0x60
#define ATA_CMD_READ_MULTIPLE 0xC4
#define ATA_CMD_READ_MULTIPLE_EXT 0x29
#define ATA_CMD_READ_LOG_EXT 0x2F
#define ATA_CMD_READ_SECTORS 0x20
#define ATA_CMD_READ_SECTORS_EXT 0x24
#define ATA_CMD_READ_LONG 0x22 /* Obsoleted in ATA-4 */
#define ATA_CMD_READ_VERIFY_SECTORS 0x40
#define ATA_CMD_READ_VERIFY_SECTORS_EXT 0x42
#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xF6
#define ATA_CMD_SECURITY_ERASE_PREPARE 0xF3
#define ATA_CMD_SECURITY_ERASE_UNIT 0xF4
#define ATA_CMD_SECURITY_FREEZE_LOCK 0xF5
#define ATA_CMD_SECURITY_SET_PASSWORD 0xF1
#define ATA_CMD_SECURITY_UNLOCK 0xF2
#define ATA_CMD_SEEK 0x70
#define ATA_CMD_SET_FEATURES 0xEF
#define ATA_CMD_SET_MAX 0xF9
#define ATA_CMD_SET_MAX_EXT 0x37
#define ATA_CMD_SET_MULTIPLE_MODE 0xC6
#define ATA_CMD_SLEEP 0xE6
#define ATA_CMD_SMART 0xB0
#define ATA_CMD_SMART_READ_DATA 0xD0
#define ATA_CMD_SMART_ENABLE_DISABLE_AUTOSAVE 0xD2
#define ATA_CMD_SMART_SAVE_ATTRIBUTE_VALUES 0xD3
#define ATA_CMD_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xD4
#define ATA_CMD_SMART_READ_LOG 0xD5
#define ATA_CMD_SMART_WRITE_LOG 0xD6
#define ATA_CMD_SMART_ENABLE_OPERATIONS 0xD8
#define ATA_CMD_SMART_DISABLE_OPERATIONS 0xD9
#define ATA_CMD_SMART_RETURN_STATUS 0xDA
#define ATA_CMD_STANDBY 0xE2
#define ATA_CMD_STANDBY_IMMEDIATE 0xE0
#define ATA_CMD_WRITE_BUFFER 0xE8
#define ATA_CMD_WRITE_DMA 0xCA
#define ATA_CMD_WRITE_DMA_EXT 0x35
#define ATA_CMD_WRITE_DMA_QUEUED 0xCC
#define ATA_CMD_WRITE_DMA_QUEUED_EXT 0x36
#define ATA_CMD_WRITE_FPDMA_QUEUED 0x61
#define ATA_CMD_WRITE_MULTIPLE 0xC5
#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39
#define ATA_CMD_WRITE_SECTORS 0x30
#define ATA_CMD_WRITE_SECTORS_EXT 0x34
#define ATA_CMD_WRITE_LONG 0x32 /* Obsoleted in ATA-4 */
/*
* define SET_FEATURES sub-commands
*/
#define ATA_CMD_SF_SET_TRANSFER_MODE 0x03
#define ATA_CMD_SF_WRITE_CACHE_ENABLE 0x02
#define ATA_CMD_SF_WRITE_CACHE_DISABLE 0x82
#define ATA_CMD_SF_ENABLE_READ_LOOK_AHEAD 0xAA
#define ATA_CMD_SF_DISABLE_READ_LOOK_AHEAD 0x55
#define ATA_CMD_SF_ENABLE_REVERT_PWR_ON_DFLTS 0xCC
#define ATA_CMD_SF_DISABLE_REVERT_PWR_ON_DFLTS 0x66
#define ATA_CMD_SF_ENABLE_SATA_FEATURE 0x10
#define ATA_CMD_SF_DISABLE_SATA_FEATURE 0x90
#define SATA_CMD_SF_NON_ZERO_BUFF_OFST_IN_DMA_SETUP_FIS 0x01
#define SATA_CMD_SF_DMA_SETUP_FIS_AUTO_ACTV_OPTIMIZATION 0x02
#define SATA_CMD_SF_GUARANTEED_IN_ORDER_DATA_DELIVERY 0x04
#define SATA_CMD_SF_ASYNC_NOTIFICATION 0x05
#define SATA_CMD_SF_SOFTWARE_SETTINGS_PRESERVATION 0x06
/* Transfer mode settings for SET_FEATURES command */
#define PIO_DEFAULT 0x0
#define PIO_MODE3 0xB
#define PIO_MODE4 0xC
#define MDMA_MODE0 0x20
#define MDMA_MODE1 0x21
#define MDMA_MODE2 0x22
#define UDMA_MODE0 0x40
#define UDMA_MODE1 0x41
#define UDMA_MODE2 0x42
#define UDMA_MODE3 0x43
#define UDMA_MODE4 0x44
#define UDMA_MODE5 0x45
#define UDMA_MODE6 0x46
/* Error register definitions for the EXECUTE DEVICE DIAGNOSTIC command */
#define ATA_ERROR_DIAGNOSTIC_CODE_DEVICE0_PASSED 0x01
/* These signatures are left in the task file registers after an
* EXECUTE DEVICE DIAGNOSTIC command, and at a few other times
*/
#define COMMAND_BLOCK_SIGNATURE_ATAPI (0x00EB1401)
#define SECTOR_COUNT_SIGNATURE_ATAPI (0x01)
#define COMMAND_BLOCK_SIGNATURE_ATA (0x00000001)
#define SECTOR_COUNT_SIGNATURE_ATA (0x01)
/* CHECK POWER MODE results in Sector Count register */
#define ATA_CHECK_POWER_MODE_STANDBY (0x00)
#define ATA_CHECK_POWER_MODE_IDLE (0x80)
#define ATA_CHECK_POWER_MODE_ACTIVE_OR_IDLE (0xFF)
/* DOWNLOAD MICROCODE SUB COMMANDS */
#define ATA_DNLD_MIC_CODE_IMMED_TEMP (0x01)
#define ATA_DNLD_MIC_CODE_IMMED_FUTURE (0x07)
/*
* define typical IDE timeout values
*
* GES 02/09/01: These values will need some tweaking!!
*/
#define ATA_TIMEOUT_GEN 30 /* generic timeout is 30 seconds */
#define ATA_TIMEOUT_IDENTIFY 2 /* timeout for IDENTIFY commands */
#define ATA_TIMEOUT_READ_BUFFER 2 /* timeout for read buffer */
#define ATA_TIMEOUT_DIAG 5 /* timeout for diagnostics command */
#define ATA_TIMEOUT_STANDBY_IDLE 30 /* timeout for start/stop unit commands */
#define ATA_TIMEOUT_FLUSH_CACHE 30 /* cache flush timeout */
#define ATA_TIMEOUT_CHECK_POWER 2 /* timeout for CHECK POWER MODE */
#define ATA_TIMEOUT_DOWNLOAD_MICROCODE 120 /* wait up to 2 minute */
/*
* define the IDENTIFY DEVICE structure
*/
typedef struct _ATA_IDENTIFY_DEVICE_DATA
{
U16 GeneralConfiguration; /* 0 */
U16 LogicalCylinders; /* 1 */
U16 SpecificConfiguration; /* 2 */
U16 LogicalHeads; /* 3 */
U16 Retired4to5[2]; /* 4-5 */
U16 LogicalSectorsPerLogicalTrack; /* 6 */
U16 Reserved7to8[2]; /* 7-8 */
U16 Retired3; /* 9 */
U16 SerialNumber[10]; /* 10-19 */
U16 Retired20to21[2]; /* 20-21 */
U16 Obsolete22; /* 22 */
U16 FirmwareRevision[4]; /* 23-26 */
U16 ModelNumber[20]; /* 27-46*/
U16 MaxMultipleSize; /* 47 */
U16 Reserved48; /* 48 */
U16 Capabilities[2]; /* 49-50 */
U16 Obsolete51to52[2]; /* 51-52 */
U16 ValidWords; /* 53 */
U16 CurrentLogicalCylinders; /* 54 */
U16 CurrentLogicalHeads; /* 55 */
U16 CurrentLogicalSectorsPerTrack; /* 56 */
U16 CurrentCapacityInSectors[2]; /* 57-58 */
U16 CurrentMultipleSize; /* 59 */
U16 TotalUserSectors[2]; /* 60-61 */
U16 Obsolete62; /* 62 */
U16 MultiwordDmaMode; /* 63 */
U16 PioModesSupported; /* 64 */
U16 MinimumMultiwordDmaTransferCycleTime; /* 65 */
U16 ManufacturerRecommendedMultiwordDmaTransferCycleTime; /* 66 */
U16 MinumumPioTransferCycleTimeWithoutFlowControl; /* 67 */
U16 MinumumPioTransferCycleTimeWithFlowControl; /* 68 */
U16 Reserved69to70[2]; /* 69-70 */
U16 Reserved71to74[4]; /* 71-74 */
U16 QueueDepth; /* 75 */
U16 SerialATACapabilities; /* 76 */
U16 Reserved77; /* 77 */
U16 SerialFeaturesSupported[2]; /* 78-79 */
U16 MajorVersionNumber; /* 80 */
U16 MinorVersionNumber; /* 81 */
U16 CommandSetsSupported[3]; /* 82-84 */
U16 CommandSetsEnabled[2]; /* 85-86 */
U16 CommandSetDefaults; /* 87 */
U16 UltraDmaModes; /* 88 */
U16 TimeForSecurityErase; /* 89 */
U16 TimeForEnahncedSecurityErase; /* 90 */
U16 CurrentAdvancedPowerManagementValue; /* 91 */
U16 MasterPasswordRevisionCode; /* 92 */
U16 HardwareResetResult; /* 93 */
U16 AcousticManagement; /* 94 */ /* GWK Reserved in ATA-5 */
U16 Reserved95to99[5]; /* 95-99 */
U16 MaximumLBAfor48bitAddressing[4]; /* 100-103 */ /* GWK Reserved in ATA-5 */
U16 Reserved104to107[4]; /* 104-107 */
U16 WorldWideName[4]; /* 108-111 */
U16 Reserved112to126[15]; /* 112-126 */
U16 RemovableMediaStatusNotification; /* 127 */
U16 SecurityStatus; /* 128 */
U16 VendorSpecific[31]; /* 129-159 */
U16 CFApowerMode; /* 160 */
U16 Reserved161to175[15]; /* 161-175 */
U16 Reserves176to254[79]; /* 176-254 */
U16 IntegrityWord; /* 255 */
} ATA_IDENTIFY_DEVICE_DATA, *PTR_ATA_IDENTIFY_DEVICE_DATA;
#define ATA_IDENTIFY_DATA_FIRMWARE_REVISION_LENGTH_IN_BYTES 8
#define ATA_IDENTIFY_DATA_MODEL_NUMBER_LENGTH_IN_BYTES 40
#define ATA_IDENTIFY_DATA_SERIAL_NUMBER_LENGTH_IN_BYTES 20
#define ATA_IDENTIFY_DATA_MAJOR_VERSION_ATA_ATAPI_7 (0x0080)
#define ATA_IDENTIFY_DATA_MAJOR_VERSION_ATA_ATAPI_8 (0x0100)
#define ATA_IDENTIFY_DATA_COMMAND_SET_DEFAULT_WWN (0x0100)
#define ATA_IDENTIFY_DATA_WRITE_CACHE_ENABLED (0x0020)
#define ATA_IDENTIFY_DATA_LOOK_AHEAD_ENABLED (0x0040)
#define ATA_IDENTIFY_DATA_SMART_FEATURE_ENABLED (0x0001)
#define ATA_IDENTIFY_DATA_SATA_SUP_FEAT_SFT_SET_PRES (0x0040)
/*
* define the IDENTIFY PACKET DEVICE structure for ATAPI
*/
typedef struct _ATA_IDENTIFY_PACKET_DEVICE_DATA
{
U16 GeneralConfiguration; /* 0 */
U16 Reserved01; /* 1 */
U16 UniqueConfiguration; /* 2 */
U16 Reserved03to09[7]; /* 3-9 */
U16 SerialNumber[10]; /* 10-19 */
U16 Retired20to22[3]; /* 20-22 */
U16 FirmwareRevision[4]; /* 23-26 */
U16 ModelNumber[20]; /* 27-46*/
U16 Reserved47to48[2]; /* 47-48 */
U16 Capabilities[2]; /* 49-50 */
U16 Obsolete51to52[2]; /* 51-52 */
U16 ValidWords; /* 53 */
U16 Reserved54to62[9]; /* 54-62 */
U16 MultiwordDmaMode; /* 63 */
U16 PioModesSupported; /* 64 */
U16 MinimumMultiwordDmaTransferCycleTime; /* 65 */
U16 ManufacturerRecommendedMultiwordDmaTransferCycleTime; /* 66 */
U16 MinumumPioTransferCycleTimeWithoutFlowControl; /* 67 */
U16 MinumumPioTransferCycleTimeWithFlowControl; /* 68 */
U16 Reserved69to70[2]; /* 69-70 */
U16 TypicalTimePacketCmdToBusRelease; /* 71 */
U16 TypicalTimeServiceToBSYCleared; /* 72 */
U16 Reserved73to74[2]; /* 73-74 */
U16 QueueDepth; /* 75 */
U16 SerialATACapabilities; /* 76 */
U16 Reserved77to79[3]; /* 77-79 */
U16 MajorVersionNumber; /* 80 */
U16 MinorVersionNumber; /* 81 */
U16 CommandSetsSupported[3]; /* 82-84 */
U16 CommandSetsEnabled[2]; /* 85-86 */
U16 CommandSetDefaults; /* 87 */
U16 UltraDmaModes; /* 88 */
U16 Reserved89to92[4]; /* 89-92 */
U16 HardwareResetResult; /* 93 */
U16 AcousticManagement; /* 94 */ /* GWK Reserved in ATA-5 */
U16 Reserved95to124[30]; /* 95-124 */
U16 AtapeByteCount0Behavior; /* 125 */
U16 Obsolete126; /* 126 */
U16 RemovableMediaStatusNotification; /* 127 */
U16 SecurityStatus; /* 128 */
U16 VendorSpecific129to159[31]; /* 129-159 */
U16 ReservedForCFA160to175[16]; /* 160-175 */
U16 Reserved176to254[79]; /* 176-254 */
U16 IntegrityWord; /* 255 */
} ATA_IDENTIFY_PACKET_DEVICE_DATA, *PTR_ATA_IDENTIFY_PACKET_DEVICE_DATA;
#define ATA_IDENTIFY_PACKET_DATA_FIRMWARE_REVISION_LENGTH_IN_BYTES 8
#define ATA_IDENTIFY_PACKET_DATA_MODEL_NUMBER_LENGTH_IN_BYTES 40
#define ATA_IDENTIFY_PACKET_DATA_SERIAL_NUMBER_LENGTH_IN_BYTES 20
/******************************************************************************/
/* */
/* S A T A S P E C I F I C D E F I N I T I O N S */
/* */
/******************************************************************************/
/* FIS Types */
#define FIS_TYPE_REGISTER_HOST_TO_DEVICE 0x27
#define FIS_TYPE_REGISTER_DEVICE_TO_HOST 0x34
#define FIS_TYPE_SET_DEVICE_BITS_DEVICE_TO_HOST 0xA1
#define FIS_TYPE_DMA_ACTIVATE_DEVICE_TO_HOST 0x39
#define FIS_TYPE_DMA_SETUP_BIDIRECTIONAL 0x41
#define FIS_TYPE_BIST_ACTIVATE_BIDIRECTIONAL 0x58
#define FIS_TYPE_PIO_SETUP_DEVICE_TO_HOST 0x5F
#define FIS_TYPE_DATA_BIDIRECTIONAL 0x46
/* FIS Command/Control Bit Definitions */
#define FIS_COMMAND_CONTROL_COMMAND 0x1
#define FIS_COMMAND_CONTROL_CONTROL 0x0
/* FIS Interrupt Bit Definitions */
#define FIS_INTERRUPT_TRUE 0x1
#define FIS_INTERRUPT_FALSE 0x0
/* FIS Direction Bit Definitions */
#define FIS_DIRECTION_TRANSMITTER_TO_RECEIVER 0x1
#define FIS_DIRECTION_RECEIVER_TO_TRANSMITTER 0x0
/*
* This is the mapping of how the various fields in the host to device FIS are used
* for CHS, LBA28-bit,and LBA48-bit modes. Use the union on the register FIS
* types to select.
*
*
* CHS LBA28 LBAEXP48
* --- ----- --------
* 0x00 U8 FISType; U8 FISType; U8 FISType;
* 0x01 U32 Reserved01Bits0to6 :7; U32 Reserved01Bits0to6 :7; U32 Reserved01Bits0to6 :7;
* U32 CommandBit :1; U32 CommandBit :1; U32 CommandBit :1;
* 0x02 U8 Command; U8 Command; U8 Command;
* 0x03 U8 Features; U8 Features; U8 Features;
* 0x04 U8 SectorNumber; U8 LBALow_0_7; U8 LBALow_0_7;
* 0x05 U8 CylLow; U8 LBAMid_8_15; U8 LBAMid_8_15;
* 0x06 U8 CylHigh; U8 LBAHigh_16_23; U8 LBAHigh_16_23;
* 0x07 U8 DeviceHead; U8 DeviceAndLBA24_27; U8 Device;
* 0x08 U8 SectorNumberExp; U8 SectorNumberExp; U8 LBALowExp_24_31;
* 0x09 U8 CylLowExp; U8 CylLowExp; U8 LBAMidExp_32_39;
* 0x0A U8 CylHighExp; U8 CylHighExp; U8 LBAHighExp_40_47;
* 0x0B U8 FeaturesExp; U8 FeaturesExp; U8 FeaturesExp;
* 0x0C U8 SectorCount; U8 SectorCount; U8 SectorCount0_7;
* 0x0D U8 SectorCountExp; U8 SectorCountExp; U8 SectorCountExp8_15;
* 0x0E U8 Reserved0E; U8 Reserved0E; U8 Reserved0E;
* 0x0F U8 Control; U8 Control; U8 Control;
* 0x10 U32 Reserved10to14; U32 Reserved10to14; U32 Reserved10to14;
*/
/*
* SATA Register - Host To Device FIS for CHS addressing
*/
typedef struct _REGISTER_HOST_TO_DEVICE_FIS_CHS
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 CommandBit :1; /* 0x01 */
U8 Reserved01Bits0to6 :7;
#else /* little endian */
U8 Reserved01Bits0to6 :7; /* 0x01 */
U8 CommandBit :1;
#endif
U8 Command; /* 0x02 */
U8 Features; /* 0x03 */
U8 SectorNumber; /* 0x04 */
U8 CylLow; /* 0x05 */
U8 CylHigh; /* 0x06 */
U8 DeviceHead; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylLowExp; /* 0x09 */
U8 CylHighExp; /* 0x0A */
U8 FeaturesExp; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Control; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_HOST_TO_DEVICE_FIS_CHS, *PTR_REGISTER_HOST_TO_DEVICE_FIS_CHS;
/*
* SATA Register - Host To Device FIS for LBA 28-bit addressing
*/
typedef struct _REGISTER_HOST_TO_DEVICE_FIS_LBA28
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 CommandBit :1; /* 0x01 */
U8 Reserved01Bits0to6 :7;
#else /* little endian */
U8 Reserved01Bits0to6 :7; /* 0x01 */
U8 CommandBit :1;
#endif
U8 Command; /* 0x02 */
U8 Features; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 LBAMid_8_15; /* 0x05 */
U8 LBAHigh_16_23; /* 0x06 */
U8 DeviceAndLBA24_27; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylLowExp; /* 0x09 */
U8 CylHighExp; /* 0x0A */
U8 FeaturesExp; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Control; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_HOST_TO_DEVICE_FIS_LBA28, *PTR_REGISTER_HOST_TO_DEVICE_FIS_LBA28;
/*
* SATA Register - Host To Device FIS for LBA 48-bit addressing
*/
typedef struct _REGISTER_HOST_TO_DEVICE_FIS_LBA48
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 CommandBit :1; /* 0x01 */
U8 Reserved01Bits0to6 :7;
#else /* little endian */
U8 Reserved01Bits0to6 :7; /* 0x01 */
U8 CommandBit :1;
#endif
U8 Command; /* 0x02 */
U8 Features; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 LBAMid_8_15; /* 0x05 */
U8 LBAHigh_16_23; /* 0x06 */
U8 Device; /* 0x07 */
U8 LBALowExp_24_31; /* 0x08 */
U8 LBAMidExp_32_39; /* 0x09 */
U8 LBAHighExp_40_47; /* 0x0A */
U8 FeaturesExp; /* 0x0B */
U8 SectorCount0_7; /* 0x0C */
U8 SectorCountExp8_15; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Control; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_HOST_TO_DEVICE_FIS_LBA48, *PTR_REGISTER_HOST_TO_DEVICE_FIS_LBA48;
/*
* SATA Register - Host To Device FIS for Packet (ATAPI) Commands
*/
typedef struct REGISTER_HOST_TO_DEVICE_FIS_PACKET
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 CommandBit :1; /* 0x01 */
U8 Reserved01Bits0to6 :7;
#else /* little endian */
U8 Reserved01Bits0to6 :7; /* 0x01 */
U8 CommandBit :1;
#endif
U8 Command; /* 0x02 */
U8 Features; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 ByteCountLow; /* 0x05 */
U8 ByteCountHigh; /* 0x06 */
U8 DeviceSelect; /* 0x07 */
U8 LBALowExp_24_31; /* 0x08 */
U8 LBAMidExp_32_39; /* 0x09 */
U8 LBAHighExp_40_47; /* 0x0A */
U8 FeaturesExp; /* 0x0B */
U8 SectorCount0_7; /* 0x0C */
U8 SectorCountExp8_15; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Control; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_HOST_TO_DEVICE_FIS_PACKET, *PTR_REGISTER_HOST_TO_DEVICE_FIS_PACKET;
/*
* SATA Register - Host To Device FIS
*/
typedef union _REGISTER_HOST_TO_DEVICE_FIS
{
REGISTER_HOST_TO_DEVICE_FIS_CHS Chs;
REGISTER_HOST_TO_DEVICE_FIS_LBA28 Lba28;
REGISTER_HOST_TO_DEVICE_FIS_LBA48 Lba48;
REGISTER_HOST_TO_DEVICE_FIS_PACKET Packet;
} REGISTER_HOST_TO_DEVICE_FIS, *PTR_REGISTER_HOST_TO_DEVICE_FIS;
/*
* SATA Register - Device To Host FIS for Chs addressing
*/
typedef struct _REGISTER_DEVICE_TO_HOST_FIS_CHS
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bits0to5 :6;
#else /* little endian */
U8 Reserved01Bits0to5 :6; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 Status; /* 0x02 */
U8 Error; /* 0x03 */
U8 SectorNumber; /* 0x04 */
U8 CylLow; /* 0x05 */
U8 CylHigh; /* 0x06 */
U8 DeviceHead; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylLowExp; /* 0x09 */
U8 CylHighExp; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Reseved0F; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_DEVICE_TO_HOST_FIS_CHS, *PTR_REGISTER_DEVICE_TO_HOST_FIS_CHS;
/*
* SATA Register - Device To Host FIS for LBA 28-bit
*/
typedef struct _REGISTER_DEVICE_TO_HOST_FIS_LBA28
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bits0to5 :6;
#else /* little endian */
U8 Reserved01Bits0to5 :6; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 Status; /* 0x02 */
U8 Error; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 LBAMid_8_15; /* 0x05 */
U8 LBAHigh_16_23; /* 0x06 */
U8 DeviceAndLBA24_27; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylLowExp; /* 0x09 */
U8 CylHighExp; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Reseved0F; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_DEVICE_TO_HOST_FIS_LBA28, *PTR_REGISTER_DEVICE_TO_HOST_FIS_LBA28;
/*
* SATA Register - Device To Host FIS for LBA 48-bit
*/
typedef struct _REGISTER_DEVICE_TO_HOST_FIS_LBA48
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bits0to5 :6;
#else /* little endian */
U8 Reserved01Bits0to5 :6; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 Status; /* 0x02 */
U8 Error; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 LBAMid_8_15; /* 0x05 */
U8 LBAHigh_16_23; /* 0x06 */
U8 Device; /* 0x07 */
U8 LBALowExp_24_31; /* 0x08 */
U8 LBAMidExp_32_39; /* 0x09 */
U8 LBAHighExp_40_47; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 SectorCount0_7; /* 0x0C */
U8 SectorCountExp8_15; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Reseved0F; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_DEVICE_TO_HOST_FIS_LBA48, *PTR_REGISTER_DEVICE_TO_HOST_FIS_LBA48;
/*
* SATA Register - Device To Host FIS for Packet (ATAPI) Commands
*/
typedef struct _REGISTER_DEVICE_TO_HOST_FIS_PACKET
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bits0to5 :6;
#else /* little endian */
U8 Reserved01Bits0to5 :6; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 AtapiStatus; /* 0x02 */
U8 Error; /* 0x03 */
U8 LBALow_0_7; /* 0x04 */
U8 ByteCountLow; /* 0x05 */
U8 ByteCountHigh; /* 0x06 */
U8 DeviceSelect; /* 0x07 */
U8 LBALowExp_24_31; /* 0x08 */
U8 LBAMidExp_32_39; /* 0x09 */
U8 LBAHighExp_40_47; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 InterruptReason; /* 0x0C */
U8 SectorCountExp8_15; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 Reseved0F; /* 0x0F */
U32 Reserved10to14; /* 0x10 */
} REGISTER_DEVICE_TO_HOST_FIS_PACKET, *PTR_REGISTER_DEVICE_TO_HOST_FIS_PACKET;
/*
* SATA Register - Device To Host FIS
*/
typedef union _REGISTER_DEVICE_TO_HOST_FIS
{
REGISTER_DEVICE_TO_HOST_FIS_CHS Chs;
REGISTER_DEVICE_TO_HOST_FIS_LBA28 Lba28;
REGISTER_DEVICE_TO_HOST_FIS_LBA48 Lba48;
REGISTER_DEVICE_TO_HOST_FIS_PACKET Packet;
} REGISTER_DEVICE_TO_HOST_FIS, *PTR_REGISTER_DEVICE_TO_HOST_FIS;
/*
* SATA Set Device Bits - Device To Host FIS
*/
typedef struct _SET_DEVICE_BITS_DEVICE_TO_HOST_FIS
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Notification :1; /* 0x01 */
U8 Interrupt :1;
U8 Reserved01Bits0to5 :6;
U8 Reserved02Bit7 :1; /* 0x02 */
U8 StatusHi :3;
U8 Reserved02Bit3 :1;
U8 StatusLo :3;
#else /* little endian */
U8 Reserved01Bits0to5 :6; /* 0x01 */
U8 Interrupt :1;
U8 Notification :1;
U8 StatusLo :3; /* 0x02 */
U8 Reserved02Bit3 :1;
U8 StatusHi :3;
U8 Reserved02Bit7 :1;
#endif
U8 Error; /* 0x03 */
U32 SActive; /* 0x04 */
} SET_DEVICE_BITS_DEVICE_TO_HOST_FIS, *PTR_SET_DEVICE_BITS_DEVICE_TO_HOST_FIS;
/*
* SATA DMA Activate - Device To Host FIS
*/
typedef struct _DMA_ACTIVATE_DEVICE_TO_HOST_FIS
{
U8 FISType; /* 0x00 */
U8 Reserved01; /* 0x01 */
U8 Reserved02; /* 0x02 */
U8 Reserved03; /* 0x03 */
} DMA_ACTIVATE_DEVICE_TO_HOST_FIS, *PTR_DMA_ACTIVATE_DEVICE_TO_HOST_FIS;
/*
* SATA DMA Setup (Bi-directional) FIS
*/
typedef struct _DMA_SETUP_FIS
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Direction :1;
U8 Reserved01Bits0to4 :5;
#else /* little endian */
U8 Reserved01Bits0to4 :5; /* 0x01 */
U8 Direction :1;
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 Reserved02; /* 0x02 */
U8 Reserved03; /* 0x03 */
U32 DMABufferIdentifierLow; /* 0x04 */
U32 DMABufferIdentifierHigh; /* 0x08 */
U32 Reserved0Cto0F; /* 0x0C */
U32 DMABufferOffset; /* 0x10 */
U32 DMATransferCount; /* 0x14 */
U32 Reserved18; /* 0x18 */
} DMA_SETUP_FIS, *PTR_DMA_SETUP_FIS;
/*
* SATA BIST Activate FIS - I don't believe we suppor this ?
*/
/*
* SATA PIO Setup - Device To Host FIS
*/
typedef struct _PIO_SETUP_DEVICE_TO_HOST_FIS
{
U8 FISType; /* 0x00 */
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 Reserved01Bit7 :1; /* 0x01 */
U8 Interrupt :1;
U8 Direction :1;
U8 Reserved01Bits0to4 :5;
#else /* little endian */
U8 Reserved01Bits0to4 :5; /* 0x01 */
U8 Direction :1;
U8 Interrupt :1;
U8 Reserved01Bit7 :1;
#endif
U8 Status; /* 0x02 */
U8 Error; /* 0x03 */
U8 SectorNumber; /* 0x04 */
U8 CylLow; /* 0x05 */
U8 CylHigh; /* 0x06 */
U8 DeviceHead; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylLowExp; /* 0x09 */
U8 CylHighExp; /* 0x0A */
U8 Reserved0B; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved0E; /* 0x0E */
U8 E_Status; /* 0x0F */
U16 TransferCount; /* 0x10 */
U16 Reserved12to13; /* 0x12 */
} PIO_SETUP_DEVICE_TO_HOST_FIS, *PTR_PIO_SETUP_DEVICE_TO_HOST_FIS;
/* PIO Setup Direction Bit */
#define PIO_SETUP_DIRECTION_HOST_TO_DEVICE (0)
#define PIO_SETUP_DIRECTION_DEVICE_TO_HOST (1)
/*
* SATA Data - (Bi-directional) FIS
*/
typedef struct _DATA_FIS
{
U8 FISType; /* 0x00 */
U8 Reserved01; /* 0x01 */
U8 Reserved02; /* 0x02 */
U8 Reserved03; /* 0x03 */
U32 Data[1]; /* 0x04 */
/* Note the data is variable in length */
} DATA_FIS, *PTR_DATA_FIS;
/* This is a union of all the SATA FIS's */
typedef union _PL_SATA_FIS_UNION
{
REGISTER_HOST_TO_DEVICE_FIS HtoDFIS;
REGISTER_DEVICE_TO_HOST_FIS DtoHFIS;
SET_DEVICE_BITS_DEVICE_TO_HOST_FIS SetDeviceDtoHFIS;
DMA_ACTIVATE_DEVICE_TO_HOST_FIS DmaActivateDtoHFIS;
DMA_SETUP_FIS DmaSetupFIS;
PIO_SETUP_DEVICE_TO_HOST_FIS PioSetupDtoHFIS;
DATA_FIS DataFIS;
} PL_SATA_FIS_UNION, * PTR_PL_SATA_FIS_UNION;
typedef struct _READ_LOG_EXT_PAGE_10_DATA
{
#if defined( __LSIUTIL_BIG_ENDIAN__ )
U8 NQ :1; /* 0x00 */
U8 Reserved00Bit5to6 :2;
U8 Tag :5;
#else /* little endian */
U8 Tag :5; /* 0x00 */
U8 Reserved00Bit5to6 :2;
U8 NQ :1;
#endif
U8 Reserved01; /* 0x01 */
U8 Status; /* 0x02 */
U8 Error; /* 0x03 */
U8 SectorNumber; /* 0x04 */
U8 CylinderLow; /* 0x05 */
U8 CylinderHigh; /* 0x06 */
U8 DevHead; /* 0x07 */
U8 SectorNumberExp; /* 0x08 */
U8 CylinderLowExp; /* 0x09 */
U8 CylinderHighExp; /* 0x0A */
U8 Reserved11; /* 0x0B */
U8 SectorCount; /* 0x0C */
U8 SectorCountExp; /* 0x0D */
U8 Reserved14to511[1]; /* 0x0E */
} READ_LOG_EXT_PAGE_10_DATA, *PTR_READ_LOG_EXT_PAGE_10_DATA;
#endif /* End of #if ATA_H_SOURCE */

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/*++ BUILD Version: 0004 // Increment this if a change has global effects
Copyright (c) 1992-1999 Microsoft Corporation
Module Name:
devioctl.h
Abstract:
This module contains
Author:
Andre Vachon (andreva) 21-Feb-1992
Revision History:
--*/
// begin_winioctl
#ifndef _DEVIOCTL_
#define _DEVIOCTL_
// begin_ntddk begin_wdm begin_nthal begin_ntifs
//
// Define the various device type values. Note that values used by Microsoft
// Corporation are in the range 0-32767, and 32768-65535 are reserved for use
// by customers.
//
#define DEVICE_TYPE ULONG
#define FILE_DEVICE_BEEP 0x00000001
#define FILE_DEVICE_CD_ROM 0x00000002
#define FILE_DEVICE_CD_ROM_FILE_SYSTEM 0x00000003
#define FILE_DEVICE_CONTROLLER 0x00000004
#define FILE_DEVICE_DATALINK 0x00000005
#define FILE_DEVICE_DFS 0x00000006
#define FILE_DEVICE_DISK 0x00000007
#define FILE_DEVICE_DISK_FILE_SYSTEM 0x00000008
#define FILE_DEVICE_FILE_SYSTEM 0x00000009
#define FILE_DEVICE_INPORT_PORT 0x0000000a
#define FILE_DEVICE_KEYBOARD 0x0000000b
#define FILE_DEVICE_MAILSLOT 0x0000000c
#define FILE_DEVICE_MIDI_IN 0x0000000d
#define FILE_DEVICE_MIDI_OUT 0x0000000e
#define FILE_DEVICE_MOUSE 0x0000000f
#define FILE_DEVICE_MULTI_UNC_PROVIDER 0x00000010
#define FILE_DEVICE_NAMED_PIPE 0x00000011
#define FILE_DEVICE_NETWORK 0x00000012
#define FILE_DEVICE_NETWORK_BROWSER 0x00000013
#define FILE_DEVICE_NETWORK_FILE_SYSTEM 0x00000014
#define FILE_DEVICE_NULL 0x00000015
#define FILE_DEVICE_PARALLEL_PORT 0x00000016
#define FILE_DEVICE_PHYSICAL_NETCARD 0x00000017
#define FILE_DEVICE_PRINTER 0x00000018
#define FILE_DEVICE_SCANNER 0x00000019
#define FILE_DEVICE_SERIAL_MOUSE_PORT 0x0000001a
#define FILE_DEVICE_SERIAL_PORT 0x0000001b
#define FILE_DEVICE_SCREEN 0x0000001c
#define FILE_DEVICE_SOUND 0x0000001d
#define FILE_DEVICE_STREAMS 0x0000001e
#define FILE_DEVICE_TAPE 0x0000001f
#define FILE_DEVICE_TAPE_FILE_SYSTEM 0x00000020
#define FILE_DEVICE_TRANSPORT 0x00000021
#define FILE_DEVICE_UNKNOWN 0x00000022
#define FILE_DEVICE_VIDEO 0x00000023
#define FILE_DEVICE_VIRTUAL_DISK 0x00000024
#define FILE_DEVICE_WAVE_IN 0x00000025
#define FILE_DEVICE_WAVE_OUT 0x00000026
#define FILE_DEVICE_8042_PORT 0x00000027
#define FILE_DEVICE_NETWORK_REDIRECTOR 0x00000028
#define FILE_DEVICE_BATTERY 0x00000029
#define FILE_DEVICE_BUS_EXTENDER 0x0000002a
#define FILE_DEVICE_MODEM 0x0000002b
#define FILE_DEVICE_VDM 0x0000002c
#define FILE_DEVICE_MASS_STORAGE 0x0000002d
#define FILE_DEVICE_SMB 0x0000002e
#define FILE_DEVICE_KS 0x0000002f
#define FILE_DEVICE_CHANGER 0x00000030
#define FILE_DEVICE_SMARTCARD 0x00000031
#define FILE_DEVICE_ACPI 0x00000032
#define FILE_DEVICE_DVD 0x00000033
#define FILE_DEVICE_FULLSCREEN_VIDEO 0x00000034
#define FILE_DEVICE_DFS_FILE_SYSTEM 0x00000035
#define FILE_DEVICE_DFS_VOLUME 0x00000036
#define FILE_DEVICE_SERENUM 0x00000037
#define FILE_DEVICE_TERMSRV 0x00000038
#define FILE_DEVICE_KSEC 0x00000039
#define FILE_DEVICE_FIPS 0x0000003A
//
// Macro definition for defining IOCTL and FSCTL function control codes. Note
// that function codes 0-2047 are reserved for Microsoft Corporation, and
// 2048-4095 are reserved for customers.
//
#define CTL_CODE( DeviceType, Function, Method, Access ) ( \
((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method) \
)
//
// Macro to extract device type out of the device io control code
//
#define DEVICE_TYPE_FROM_CTL_CODE(ctrlCode) (((ULONG)(ctrlCode & 0xffff0000)) >> 16)
//
// Define the method codes for how buffers are passed for I/O and FS controls
//
#define METHOD_BUFFERED 0
#define METHOD_IN_DIRECT 1
#define METHOD_OUT_DIRECT 2
#define METHOD_NEITHER 3
//
// Define the access check value for any access
//
//
// The FILE_READ_ACCESS and FILE_WRITE_ACCESS constants are also defined in
// ntioapi.h as FILE_READ_DATA and FILE_WRITE_DATA. The values for these
// constants *MUST* always be in sync.
//
//
// FILE_SPECIAL_ACCESS is checked by the NT I/O system the same as FILE_ANY_ACCESS.
// The file systems, however, may add additional access checks for I/O and FS controls
// that use this value.
//
#define FILE_ANY_ACCESS 0
#define FILE_SPECIAL_ACCESS (FILE_ANY_ACCESS)
#define FILE_READ_ACCESS ( 0x0001 ) // file & pipe
#define FILE_WRITE_ACCESS ( 0x0002 ) // file & pipe
// end_ntddk end_wdm end_nthal end_ntifs
#endif // _DEVIOCTL_
// end_winioctl

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#ifndef _DMI_IOCTL_H_
#define _DMI_IOCTL_H_
/***************************************************************************
* *
* Copyright 1998 LSI Logic Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Logic. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Logic Corporation. *
* *
***************************************************************************/
/* Name: DMI_IOCTL.H
* Title: Solaris O/S Character mode IOCTL definitions
* Programmer: Russell A. Johnson
* Creation Date: May 26, 1998
*
* Version History
* ---------------
*
* Date Who? Description
* -------- ---- -------------------------------------------------------
#BeginRevision
* 05/17/00 RAJ Added bus mode support for fibre channel devices.
* 12/19/99 RAJ Added new flags for scsi-3 options.
* 11/09/98 RAJ Changed copyright notice to LSI Logic.
#EndRevision
* Version 4.02.01
* 07/22/98 RAJ Added some more data to the DMI data structure. This
* includes the PCI bus number, device number, and function
* number. Also added a major version number for the data
* structure. That version number indicates major changes.
* When it changes then the entire data format may have
* changed. See the comments below for more details.
#EndRevision
* Version 4.00.04
* 05/26/98 RAJ Initial version.
#EndRevision
*
#BeginDescription
*
* This file contains the Solaris 2.6 character mode driver interface
* definitions needed in order to provide IOCTL's for our SCSI HBA driver.
*
#EndDescription
*
*-------------------------------------------------------------------------
*/
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
* HEADER FILE DEPENDANCIES
*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
*
* This file is dependent on the following files:
*
* SALIOS.H - type defintions UINT8, UINT16, UINT32, UINT64
*/
/* The following data is for our character mode ioctl interface. Per the
* Solaris standard mechanism, we define SYMIOCTL as a unique number in the
* upper 8 bits and a command value in the lower 8 bits.
*/
#define SYMIOCTL ('H' << 8)
#define SYMIOCTL_GET_DMI_DATA (SYMIOCTL | 1)
#define SYMIOCTL_GET_TIMERS (SYMIOCTL | 2)
#define SYMIOCTL_UPDATE_FLASH (SYMIOCTL | 3)
#define SYMIOCTL_RESET_ADAPTER (SYMIOCTL | 4)
#define SYMIOCTL_GET_PROPERTY (SYMIOCTL | 5)
#define SYMIOCTL_PASS_THRU (SYMIOCTL | 6)
#define SYMIOCTL_REG_ACCESS (SYMIOCTL | 7)
#define SYMIOCTL_EVENT_QUERY (SYMIOCTL | 8)
#define SYMIOCTL_EVENT_ENABLE (SYMIOCTL | 9)
#define SYMIOCTL_EVENT_REPORT (SYMIOCTL | 10)
#define SYMIOCTL_GET_PCI_INFO (SYMIOCTL | 11)
#define SYMIOCTL_BTDH_MAPPING (SYMIOCTL | 12)
#define SYMIOCTL_DIAG_ACTION (SYMIOCTL | 13)
#define SYMIOCTL_PASS_THRU_TIMEOUT (SYMIOCTL | 14)
/* The following are our ioctl() return status values. If everything went
* well, we return good status. If the buffer length sent to us is too short
* we return a status to tell the user.
*/
#define SYMIOCTL_STATUS_GOOD 0
#define SYMIOCTL_STATUS_LEN_TOO_SHORT 1
/* The data structures defined in this file are marked with a data structure
* length and data structure version. The length value is the first value in
* the structure and is used to make sure the buffer is large enough for
* communication between the driver and the application. The version number is
* a major version number. If the data structure changes and only has a new
* element appended, then the version number will remain the same but the
* length will increase. If the data structure changes in any other way, such
* as re-arranging all of its elements, then the version number will increase.
*
* The following macro defines the current version number of the data
* structure.
*/
#define SYMHI_DMI_DATA_VERSION 1
/* The following is the SYMIOCTL_GET_DMI_DATA data structure. This data
* structure is setup so that we hopefully are properly aligned for both 32-bit
* and 64-bit mode applications.
*
* StructureLength - This value is the amount of data the caller has allocated
* for the structure when they first call us. After we have filled in the
* structure, this indicates the length our data structure is.
*
* MajorVersion - This value is used by the driver to tell the application what
* version of the data structure is being provided. It only changes if the
* data ordering of the data below is changed.
*
* MinSyncPeriodNs - This is the minimum period in nano-seconds (ns) that we
* will negotiate for on this adapter. The smaller value the faster
* synchronous speed except if this value is zero then asynchronous transfers
* is all we support.
*
* MaxWidth - This value indicates the maximum width this bus can be used as.
* If the PciDeviceId indicates a width capability of 16 devices and this is
* set to 8 devices then the PCI Subsystem ID value has limited our use of this
* adapter to 8 devices. This value also indicates the number of valid
* elements in the DevSpeed[] and DevWidth[] array's.
*
* HostScsiId - This is the host adapter SCSI ID being used by this adapter.
*
* PciBusNumber - The number of the PCI bus this adapter is on. If for some
* reason the driver is unable to determine the bus number, device number, or
* function number, these values will be set to 0xFF.
*
* PciDeviceNumber - The PCI device number for this device.
*
* PciFunctionNumber - The PCI function number for this device.
*
* PciDeviceId - This is the PCI device ID from PCI configuration space for
* this adapter.
*
* PciRevision - This is the PCI revision value from PCI configuration space
* for this adapter.
*
* HwBusMode - This value indicates the mode the bus is currently in. See the
* SYM_HW_BUS_MODE_xx macros.
*
* DevSpeed - This array is indexed by the target ID and indicates the
* currently negotiated synchronous speed in nano-seconds (ns). A value of
* zero ns indicates asynchronous mode.
*
* DevWidth - This array is indexed by the target ID and indicates the
* currently negotiated width in bits. A value of 8 indicates narrow mode, a
* value of 16 indicates wide.
*
* DriverVersion - This is an ascii null-terminated string indicating the
* version of this driver.
*
* DevFlags - This array is indexed by the target ID and indicates the
* currently negotiated options such as DT and async protection capabilities.
*/
#pragma pack(1)
typedef struct _SYMHI_DMI_DATA
{ /* Offset */
UINT32 StructureLength; /* 0x00..0x03 */
UINT32 Reserved1; /* 0x04..0x07 */
UINT32 MajorVersion; /* 0x08..0x0B */
UINT16 MinSyncPeriodNs; /* 0x0C..0x0D */
UINT8 MaxWidth; /* 0x0E */
UINT8 HostScsiId; /* 0x0F */
UINT8 PciBusNumber; /* 0x10 */
UINT8 PciDeviceNumber; /* 0x11 */
UINT8 PciFunctionNumber; /* 0x12 */
UINT8 Reserved2; /* 0x13 */
UINT16 PciDeviceId; /* 0x14..0x15 */
UINT8 PciRevision; /* 0x16 */
UINT8 HwBusMode; /* 0x17 */
UINT8 Reserved3[8]; /* 0x18..0x1F */
#if defined TARGET_MPTx
/* MPI adapters can have many more devices per SCSI bus than non-MPI
* adapters.
*/
UINT16 DevSpeed[256]; /* 0x20..0x21F */
UINT8 DevWidth[256]; /* 0x220..0x31F */
UINT32 DevFlags[256]; /* 0x320..0x71F */
char DriverVersion[80]; /* 0x720..0x76F */
#elif defined TARGET_HIHW || defined TARGET_SRHW
UINT16 DevSpeed[16]; /* 0x20..0x3F */
UINT8 DevWidth[16]; /* 0x40..0x4F */
char DriverVersion[80]; /* 0x50..0x9F */
UINT32 DevFlags[16]; /* 0xA0..0xDF */
#else
#error "Unknown hardware type"
#endif /* defined TARGET_xxx */
} SYMHI_DMI_DATA, * PTR_SYMHI_DMI_DATA;
#pragma pack()
/* The following are definitions for the value of HwBusMode in the
* SYMHI_DMI_DATA data structure.
*
* SYM_HW_BUS_MODE_UNKNOWN - The bus mode is not known yet
* SYM_HW_BUS_MODE_SINGLE - The bus is in single ended mode
* SYM_HW_BUS_MODE_HVD - The bus is in high voltage differential mode
* SYM_HW_BUS_MODE_LVD - The bus is in low voltage differential mode
* SYM_HW_BUS_MODE_FC - The bus is a fibre channel bus
*/
#define SYM_HW_BUS_MODE_UNKNOWN (0x00)
#define SYM_HW_BUS_MODE_SINGLE (0x01)
#define SYM_HW_BUS_MODE_HVD (0x02)
#define SYM_HW_BUS_MODE_LVD (0x03)
#define SYM_HW_BUS_MODE_FC (0x04)
/* The following are definitions for the DevFlags[] array. Each bit is set
* only when the feature is currently in use for the given device.
*
* SYM_DEV_DT - Set when Dual Transfers (ie. dual edge clock in use) enabled
* SYM_DEV_ASYNC_PROT - Set when asynchronous phase protection is enabled
*/
#define SYM_DEV_DT (0x00000001)
#define SYM_DEV_ASYNC_PROT (0x00000002)
#pragma pack(1)
typedef struct _SYM_UPDATE_FLASH
{
UINT64 PtrBuffer;
UINT32 ImageChecksum;
UINT32 ImageOffset;
UINT32 ImageSize;
UINT32 ImageType;
} SYM_UPDATE_FLASH, * PTR_SYM_UPDATE_FLASH;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_GET_PROPERTY
{
UINT64 PtrName;
UINT64 PtrBuffer;
UINT32 NameLen;
UINT32 BufferLen;
UINT32 PropertyLen;
} SYM_GET_PROPERTY, * PTR_SYM_GET_PROPERTY;
#pragma pack()
#define SYM_PASS_THRU_NONE 0
#define SYM_PASS_THRU_READ 1
#define SYM_PASS_THRU_WRITE 2
#define SYM_PASS_THRU_BOTH 3
#pragma pack(1)
typedef struct _SYM_PASS_THRU
{
UINT64 PtrRequest;
UINT64 PtrReply;
UINT64 PtrData;
UINT32 RequestSize;
UINT32 ReplySize;
UINT32 DataSize;
UINT32 DataDirection;
UINT64 PtrDataOut;
UINT32 DataOutSize;
} SYM_PASS_THRU, * PTR_SYM_PASS_THRU;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_PASS_THRU_TIMEOUT
{
UINT64 PtrRequest;
UINT64 PtrReply;
UINT64 PtrData;
UINT32 RequestSize;
UINT32 ReplySize;
UINT32 DataSize;
UINT32 DataDirection;
UINT64 PtrDataOut;
UINT32 DataOutSize;
UINT32 Timeout;
} SYM_PASS_THRU_TIMEOUT, * PTR_SYM_PASS_THRU_TIMEOUT;
#pragma pack()
#define REG_IO_READ 1
#define REG_IO_WRITE 2
#define REG_MEM_READ 3
#define REG_MEM_WRITE 4
#pragma pack(1)
typedef struct _SYM_REG_ACCESS
{
UINT32 Command;
UINT32 RegOffset;
UINT32 RegData;
} SYM_REG_ACCESS, * PTR_SYM_REG_ACCESS;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_EVENT_QUERY
{
UINT32 Entries;
UINT32 Types;
} SYM_EVENT_QUERY, * PTR_SYM_EVENT_QUERY;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_EVENT_ENABLE
{
UINT32 Types;
} SYM_EVENT_ENABLE, * PTR_SYM_EVENT_ENABLE;
#pragma pack()
#if defined TARGET_MPT2
#define EVENT_ENTRY_NUM 48
#else
#define EVENT_ENTRY_NUM 2
#endif
#pragma pack(1)
typedef struct _SYM_EVENT_ENTRY
{
UINT32 Type;
UINT32 Number;
UINT32 Data[EVENT_ENTRY_NUM];
} SYM_EVENT_ENTRY, * PTR_SYM_EVENT_ENTRY;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_EVENT_REPORT
{
UINT32 Size;
SYM_EVENT_ENTRY Events[1];
} SYM_EVENT_REPORT, * PTR_SYM_EVENT_REPORT;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_PCI_INFO
{
UINT32 BusNumber;
UINT8 DeviceNumber;
UINT8 FunctionNumber;
UINT16 InterruptVector;
UINT8 PciHeader[256];
} SYM_PCI_INFO, * PTR_SYM_PCI_INFO;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_BTDH_MAPPING
{
UINT16 TargetID;
UINT16 Bus;
UINT16 DevHandle;
UINT16 Reserved;
} SYM_BTDH_MAPPING, * PTR_SYM_BTDH_MAPPING;
#pragma pack()
#pragma pack(1)
typedef struct _SYM_DIAG_ACTION
{
UINT32 Action;
UINT32 Length;
UINT64 PtrDiagAction;
UINT32 ReturnCode;
} SYM_DIAG_ACTION, * PTR_SYM_DIAG_ACTION;
#pragma pack()
#define FW_DIAGNOSTIC_BUFFER_COUNT (3)
#define FW_DIAGNOSTIC_UID_NOT_FOUND (0xFF)
#define MPI_FW_DIAG_NEW (0x806E6577)
#define MPI_FW_DIAG_TYPE_REGISTER (0x00000001)
#define MPI_FW_DIAG_TYPE_UNREGISTER (0x00000002)
#define MPI_FW_DIAG_TYPE_QUERY (0x00000003)
#define MPI_FW_DIAG_TYPE_READ_BUFFER (0x00000004)
#define MPI_FW_DIAG_TYPE_RELEASE (0x00000005)
#define MPI_FW_DIAG_INVALID_UID (0x00000000)
#define MPI_FW_DIAG_ERROR_SUCCESS (0x00000000)
#define MPI_FW_DIAG_ERROR_FAILURE (0x00000001)
#define MPI_FW_DIAG_ERROR_INVALID_PARAMETER (0x00000002)
#define MPI_FW_DIAG_ERROR_POST_FAILED (0x00000010)
#define MPI_FW_DIAG_ERROR_INVALID_UID (0x00000011)
#define MPI_FW_DIAG_ERROR_RELEASE_FAILED (0x00000012)
#define MPI_FW_DIAG_ERROR_NO_BUFFER (0x00000013)
#define MPI_FW_DIAG_ERROR_ALREADY_RELEASED (0x00000014)
#pragma pack(1)
typedef struct _MPI_FW_DIAG_REGISTER
{
UINT8 TraceLevel;
UINT8 BufferType;
UINT16 Flags;
UINT32 ExtendedType;
UINT32 ProductSpecific[4];
UINT32 RequestedBufferSize;
UINT32 UniqueId;
} MPI_FW_DIAG_REGISTER, * PTR_MPI_FW_DIAG_REGISTER;
#pragma pack()
#pragma pack(1)
typedef struct _MPI_FW_DIAG_UNREGISTER
{
UINT32 UniqueId;
} MPI_FW_DIAG_UNREGISTER, * PTR_MPI_FW_DIAG_UNREGISTER;
#pragma pack()
#define MPI_FW_DIAG_FLAG_APP_OWNED (0x0001)
#define MPI_FW_DIAG_FLAG_BUFFER_VALID (0x0002)
#define MPI_FW_DIAG_FLAG_FW_BUFFER_ACCESS (0x0004)
#pragma pack(1)
typedef struct _MPI_FW_DIAG_QUERY
{
UINT8 TraceLevel;
UINT8 BufferType;
UINT16 Flags;
UINT32 ExtendedType;
UINT32 ProductSpecific[4];
UINT32 TotalBufferSize;
UINT32 DriverAddedBufferSize;
UINT32 UniqueId;
} MPI_FW_DIAG_QUERY, * PTR_MPI_FW_DIAG_QUERY;
#pragma pack()
#pragma pack(1)
typedef struct _MPI_FW_DIAG_RELEASE
{
UINT32 UniqueId;
} MPI_FW_DIAG_RELEASE, * PTR_MPI_FW_DIAG_RELEASE;
#pragma pack()
#define MPI_FW_DIAG_FLAG_REREGISTER (0x0001)
#define MPI_FW_DIAG_FLAG_FORCE_RELEASE (0x0002)
#pragma pack(1)
typedef struct _MPI_FW_DIAG_READ_BUFFER
{
UINT8 Status;
UINT8 Reserved;
UINT16 Flags;
UINT32 StartingOffset;
UINT32 BytesToRead;
UINT32 UniqueId;
UINT32 DataBuffer[1];
} MPI_FW_DIAG_READ_BUFFER, * PTR_MPI_FW_DIAG_READ_BUFFER;
#pragma pack()
#endif

32
source/inc/getopt.h Executable file
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/***************************************************************************
* *
* Copyright 2012 LSI Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Corporation. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Corporation. *
* *
***************************************************************************
*/
#if !EFI
#include <stdio.h>
#include <stddef.h>
#include <string.h>
#endif
#ifndef _GETOPT_
#define _GETOPT_
int getopt(int argc, char *argv[], char *optstring);
extern char *optarg; /* returned arg to go with this option */
extern int optind; /* index to next argv element to process */
extern int opterr; /* should error messages be printed? */
extern int optopt;
#define BADCH ('?')
#endif /* _GETOPT */

146
source/inc/helper.h Executable file
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/***************************************************************************
* *
* Copyright 2012 LSI Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Corporation. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Corporation. *
* *
***************************************************************************
*/
#if EFIEBC
#define EFI_SPECIFICATION_VERSION 0x0001000A
#define TIANO_RELEASE_VERSION 0x00080006
#include "efibind.h"
#include "efitypes.h"
#include "eficommon.h"
#include "efiapi.h"
#include "efierror.h"
#include "efistdarg.h"
#include "efishelllib.h"
#define DevicePathToStr LibDevicePathToStr
#define LibFileInfo LibGetFileInfo
#define GenericFileInfo gEfiFileInfoGuid
#define InitializeShellApplication LibInitializeShellApplication
#define LoadedImageProtocol gEfiLoadedImageProtocolGuid
#define EFIERR_OEM(x) EFIERR(x+1000)
#define EFI_LOADED_IMAGE EFI_LOADED_IMAGE_PROTOCOL
#define EFI_FILE_IO_INTERFACE EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
#define SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID
#define EVT_TIMER EFI_EVENT_TIMER
#define va_start VA_START
#define va_arg VA_ARG
#define va_end VA_END
#define va_list VA_LIST
#else
#include "efi.h"
#include "efilib.h"
#include "efistdarg.h"
#include "shell.h"
#endif
#if EFI32
typedef unsigned int size_t;
#endif
// ctype.h
int isalnum(int c);
int isalpha(int c);
int isascii(int c);
int isblank(int c);
int iscntrl(int c);
int isdigit(int c);
int isgraph(int c);
int islower(int c);
int isprint(int c);
int ispunct(int c);
int isspace(int c);
int isupper(int c);
int isxdigit(int c);
int toupper(int c);
int tolower(int c);
// errno.h
extern int errno;
#define EFAULT 14
#define ENODEV 19
#define EINVAL 22
// fcntl.h
#define O_RDONLY 00
#define O_WRONLY 01
#define O_RDWR 02
#define O_CREAT 0100 /* not fcntl */
#define O_TRUNC 01000 /* not fcntl */
// sttdef.h
#define offsetof(s, m) (size_t)(&(((s *)0)->m))
// stdio.h
#define EOF 0
typedef void * FILE;
#define stdin (void *)1
#define stdout (void *)2
#define stderr (void *)3
int fgetc(FILE *stream);
char *fgets(char *s, int size, FILE *stream);
int getc(FILE *stream);
int getchar(void);
char *gets(char *s);
int ungetc(int c, FILE *stream);
int vsprintf(char *s, const char *format, va_list args);
int printf(const char *format, ...);
int fprintf(FILE *stream, const char *format, ...);
int sprintf(char *str, const char *format, ...);
int scanf(const char *format, ...);
int fscanf(FILE *stream, const char *format, ...);
int sscanf(const char *str, const char *format, ...);
FILE *fopen(const char *path, const char *mode);
int fclose(FILE *stream);
int fputs(const char *s, FILE *stream);
int fputc(int c, FILE *stream);
void perror(const char *s);
int fflush(FILE *stream);
// stdlib.h
void *malloc(size_t size);
void free(void *ptr);
void *realloc(void *ptr, size_t size);
void exit(int status);
int rand(void);
// string.h
void *memset(void *s, int c, size_t n);
void *memcpy(void *dest, const void *src, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
char *strcpy(char *dest, const char *src);
char *strncpy(char *dest, const char *src, size_t n);
int strcmp(const char *s1, const char *s2);
int strncmp(const char *s1, const char *s2, size_t n);
size_t strlen(const char *s);
char *strcat(char *dest, const char *src);
char *strncat(char *dest, const char *src, size_t n);
char *strchr(const char *s, int c);
char *strrchr(const char *s, int c);
// strings.h
int strcasecmp(const char *s1, const char *s2);
int strncasecmp(const char *s1, const char *s2, size_t n);
void bzero(void *s, size_t n);
void bcopy(const void *src, void *dest, size_t n);
// sys/stat.h
typedef size_t off_t;
struct stat {
off_t st_size; /* total size, in bytes */
};
int stat(const char *file_name, struct stat *buf);
int fstat(int filedes, struct stat *buf);
// time.h
typedef unsigned long time_t;
time_t time(time_t *t);
char *ctime(const time_t *t);
void mdelay(int milliseconds);
void udelay(int microseconds);
// unistd.h
typedef int ssize_t;
typedef int mode_t;
unsigned int sleep(unsigned int seconds);
int open(const char *pathname, int flags, ...);
int close(int fd);
ssize_t read(int fd, void *buf, size_t count);
ssize_t write(int fd, const void *buf, size_t count);

398
source/inc/mpt2sas_ctl.h Executable file
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/***************************************************************************
* *
* Copyright 2012 LSI Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Corporation. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Corporation. *
* *
***************************************************************************
*/
#ifndef MPT2SAS_CTL_H_INCLUDED
#define MPT2SAS_CTL_H_INCLUDED
#ifdef __KERNEL__
#include <linux/miscdevice.h>
#endif
/**
* NOTE
* FWDOWNLOAD - PR is let me know if we need to implement this
* DIAGBUFFER - PR said hold off
*/
/**
* HACK - changeme (MPT_MINOR = 220 )
*/
#ifndef MPT2SAS_MINOR
#define MPT2SAS_MINOR (MPT_MINOR + 1)
#endif
#define MPT2SAS_DEV_NAME "mpt2ctl"
#define MPT2_MAGIC_NUMBER 'L'
#define MPT2_IOCTL_DEFAULT_TIMEOUT (10) /* in seconds */
/**
* IOCTL opcodes
*/
#define MPT2IOCINFO _IOWR(MPT2_MAGIC_NUMBER, 17, \
struct mpt2_ioctl_iocinfo)
#define MPT2COMMAND _IOWR(MPT2_MAGIC_NUMBER, 20, \
struct mpt2_ioctl_command)
#ifdef CONFIG_COMPAT
#define MPT2COMMAND32 _IOWR(MPT2_MAGIC_NUMBER, 20, \
struct mpt2_ioctl_command32)
#endif
#define MPT2EVENTQUERY _IOWR(MPT2_MAGIC_NUMBER, 21, \
struct mpt2_ioctl_eventquery)
#define MPT2EVENTENABLE _IOWR(MPT2_MAGIC_NUMBER, 22, \
struct mpt2_ioctl_eventenable)
#define MPT2EVENTREPORT _IOWR(MPT2_MAGIC_NUMBER, 23, \
struct mpt2_ioctl_eventreport)
#define MPT2HARDRESET _IOWR(MPT2_MAGIC_NUMBER, 24, \
struct mpt2_ioctl_diag_reset)
#define MPT2BTDHMAPPING _IOWR(MPT2_MAGIC_NUMBER, 31, \
struct mpt2_ioctl_btdh_mapping)
/* diag buffer support */
#define MPT2DIAGREGISTER _IOWR(MPT2_MAGIC_NUMBER, 26, \
struct mpt2_diag_register)
#define MPT2DIAGRELEASE _IOWR(MPT2_MAGIC_NUMBER, 27, \
struct mpt2_diag_release)
#define MPT2DIAGUNREGISTER _IOWR(MPT2_MAGIC_NUMBER, 28, \
struct mpt2_diag_unregister)
#define MPT2DIAGQUERY _IOWR(MPT2_MAGIC_NUMBER, 29, \
struct mpt2_diag_query)
#define MPT2DIAGREADBUFFER _IOWR(MPT2_MAGIC_NUMBER, 30, \
struct mpt2_diag_read_buffer)
/**
* struct mpt2_ioctl_header - main header structure
* @ioc_number - IOC unit number
* @port_number - IOC port number
* @max_data_size - maximum number bytes to transfer on read
*/
struct mpt2_ioctl_header {
uint32_t ioc_number;
uint32_t port_number;
uint32_t max_data_size;
};
/**
* struct mpt2_ioctl_diag_reset - diagnostic reset
* @hdr - generic header
*/
struct mpt2_ioctl_diag_reset {
struct mpt2_ioctl_header hdr;
};
/**
* struct mpt2_ioctl_pci_info - pci device info
* @device - pci device id
* @function - pci function id
* @bus - pci bus id
* @segment_id - pci segment id
*/
struct mpt2_ioctl_pci_info {
union {
struct {
uint32_t device:5;
uint32_t function:3;
uint32_t bus:24;
} bits;
uint32_t word;
} u;
uint32_t segment_id;
};
#define MPT2_IOCTL_INTERFACE_SCSI (0x00)
#define MPT2_IOCTL_INTERFACE_FC (0x01)
#define MPT2_IOCTL_INTERFACE_FC_IP (0x02)
#define MPT2_IOCTL_INTERFACE_SAS (0x03)
#define MPT2_IOCTL_INTERFACE_SAS2 (0x04)
#define MPT2_IOCTL_VERSION_LENGTH (32)
/**
* struct mpt2_ioctl_iocinfo - generic controller info
* @hdr - generic header
* @adapter_type - type of adapter (spi, fc, sas)
* @port_number - port number
* @pci_id - PCI Id
* @hw_rev - hardware revision
* @sub_system_device - PCI subsystem Device ID
* @sub_system_vendor - PCI subsystem Vendor ID
* @rsvd0 - reserved
* @firmware_version - firmware version
* @bios_version - BIOS version
* @driver_version - driver version - 32 ASCII characters
* @rsvd1 - reserved
* @scsi_id - scsi id of adapter 0
* @rsvd2 - reserved
* @pci_information - pci info (2nd revision)
*/
struct mpt2_ioctl_iocinfo {
struct mpt2_ioctl_header hdr;
uint32_t adapter_type;
uint32_t port_number;
uint32_t pci_id;
uint32_t hw_rev;
uint32_t subsystem_device;
uint32_t subsystem_vendor;
uint32_t rsvd0;
uint32_t firmware_version;
uint32_t bios_version;
uint8_t driver_version[MPT2_IOCTL_VERSION_LENGTH];
uint8_t rsvd1;
uint8_t scsi_id;
uint16_t rsvd2;
struct mpt2_ioctl_pci_info pci_information;
};
/* number of event log entries */
#define MPT2SAS_CTL_EVENT_LOG_SIZE (50)
/**
* struct mpt2_ioctl_eventquery - query event count and type
* @hdr - generic header
* @event_entries - number of events returned by get_event_report
* @rsvd - reserved
* @event_types - type of events currently being captured
*/
struct mpt2_ioctl_eventquery {
struct mpt2_ioctl_header hdr;
uint16_t event_entries;
uint16_t rsvd;
uint32_t event_types[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];
};
/**
* struct mpt2_ioctl_eventenable - enable/disable event capturing
* @hdr - generic header
* @event_types - toggle off/on type of events to be captured
*/
struct mpt2_ioctl_eventenable {
struct mpt2_ioctl_header hdr;
uint32_t event_types[4];
};
#define MPT2_EVENT_DATA_SIZE (192)
/**
* struct MPT2_IOCTL_EVENTS -
* @event - the event that was reported
* @context - unique value for each event assigned by driver
* @data - event data returned in fw reply message
*/
struct MPT2_IOCTL_EVENTS {
uint32_t event;
uint32_t context;
uint8_t data[MPT2_EVENT_DATA_SIZE];
};
/**
* struct mpt2_ioctl_eventreport - returing event log
* @hdr - generic header
* @event_data - (see struct MPT2_IOCTL_EVENTS)
*/
struct mpt2_ioctl_eventreport {
struct mpt2_ioctl_header hdr;
struct MPT2_IOCTL_EVENTS event_data[1];
};
/**
* struct mpt2_ioctl_command - generic mpt firmware passthru ioclt
* @hdr - generic header
* @timeout - command timeout in seconds. (if zero then use driver default
* value).
* @reply_frame_buf_ptr - reply location
* @data_in_buf_ptr - destination for read
* @data_out_buf_ptr - data source for write
* @sense_data_ptr - sense data location
* @max_reply_bytes - maximum number of reply bytes to be sent to app.
* @data_in_size - number bytes for data transfer in (read)
* @data_out_size - number bytes for data transfer out (write)
* @max_sense_bytes - maximum number of bytes for auto sense buffers
* @data_sge_offset - offset in words from the start of the request message to
* the first SGL
* @mf[1];
*/
struct mpt2_ioctl_command {
struct mpt2_ioctl_header hdr;
uint32_t timeout;
void __user *reply_frame_buf_ptr;
void __user *data_in_buf_ptr;
void __user *data_out_buf_ptr;
void __user *sense_data_ptr;
uint32_t max_reply_bytes;
uint32_t data_in_size;
uint32_t data_out_size;
uint32_t max_sense_bytes;
uint32_t data_sge_offset;
uint8_t mf[1];
};
#ifdef CONFIG_COMPAT
struct mpt2_ioctl_command32 {
struct mpt2_ioctl_header hdr;
uint32_t timeout;
uint32_t reply_frame_buf_ptr;
uint32_t data_in_buf_ptr;
uint32_t data_out_buf_ptr;
uint32_t sense_data_ptr;
uint32_t max_reply_bytes;
uint32_t data_in_size;
uint32_t data_out_size;
uint32_t max_sense_bytes;
uint32_t data_sge_offset;
uint8_t mf[1];
};
#endif
/**
* struct mpt2_ioctl_btdh_mapping - mapping info
* @hdr - generic header
* @id - target device identification number
* @bus - SCSI bus number that the target device exists on
* @handle - device handle for the target device
* @rsvd - reserved
*
* To obtain a bus/id the application sets
* handle to valid handle, and bus/id to 0xFFFF.
*
* To obtain the device handle the application sets
* bus/id valid value, and the handle to 0xFFFF.
*/
struct mpt2_ioctl_btdh_mapping {
struct mpt2_ioctl_header hdr;
uint32_t id;
uint32_t bus;
uint16_t handle;
uint16_t rsvd;
};
/* status bits for ioc->diag_buffer_status */
#define MPT2_DIAG_BUFFER_IS_REGISTERED (0x01)
#define MPT2_DIAG_BUFFER_IS_RELEASED (0x02)
#define MPT2_DIAG_BUFFER_IS_DIAG_RESET (0x04)
/* application flags for mpt2_diag_register, mpt2_diag_query */
#define MPT2_APP_FLAGS_APP_OWNED (0x0001)
#define MPT2_APP_FLAGS_BUFFER_VALID (0x0002)
#define MPT2_APP_FLAGS_FW_BUFFER_ACCESS (0x0004)
/* flags for mpt2_diag_read_buffer */
#define MPT2_FLAGS_REREGISTER (0x0001)
#define MPT2_PRODUCT_SPECIFIC_DWORDS 23
/**
* struct mpt2_diag_register - application register with driver
* @hdr - generic header
* @reserved -
* @buffer_type - specifies either TRACE or SNAPSHOT
* @application_flags - misc flags
* @diagnostic_flags - specifies flags affecting command processing
* @product_specific - product specific information
* @requested_buffer_size - buffers size in bytes
* @unique_id - tag specified by application that is used to signal ownership
* of the buffer.
*
* This will allow the driver to setup any required buffers that will be
* needed by firmware to communicate with the driver.
*/
struct mpt2_diag_register {
struct mpt2_ioctl_header hdr;
uint8_t reserved;
uint8_t buffer_type;
uint16_t application_flags;
uint32_t diagnostic_flags;
uint32_t product_specific[MPT2_PRODUCT_SPECIFIC_DWORDS];
uint32_t requested_buffer_size;
uint32_t unique_id;
};
/**
* struct mpt2_diag_unregister - application unregister with driver
* @hdr - generic header
* @unique_id - tag uniquely identifies the buffer to be unregistered
*
* This will allow the driver to cleanup any memory allocated for diag
* messages and to free up any resources.
*/
struct mpt2_diag_unregister {
struct mpt2_ioctl_header hdr;
uint32_t unique_id;
};
/**
* struct mpt2_diag_query - query relevant info associated with diag buffers
* @hdr - generic header
* @reserved -
* @buffer_type - specifies either TRACE or SNAPSHOT
* @application_flags - misc flags
* @diagnostic_flags - specifies flags affecting command processing
* @product_specific - product specific information
* @total_buffer_size - diag buffer size in bytes
* @driver_added_buffer_size - size of extra space appended to end of buffer
* @unique_id - unique id associated with this buffer.
*
* The application will send only buffer_type and unique_id. Driver will
* inspect unique_id first, if valid, fill in all the info. If unique_id is
* 0x00, the driver will return info specified by Buffer Type.
*/
struct mpt2_diag_query {
struct mpt2_ioctl_header hdr;
uint8_t reserved;
uint8_t buffer_type;
uint16_t application_flags;
uint32_t diagnostic_flags;
uint32_t product_specific[MPT2_PRODUCT_SPECIFIC_DWORDS];
uint32_t total_buffer_size;
uint32_t driver_added_buffer_size;
uint32_t unique_id;
};
/**
* struct mpt2_diag_release - request to send Diag Release Message to firmware
* @hdr - generic header
* @unique_id - tag uniquely identifies the buffer to be released
*
* This allows ownership of the specified buffer to returned to the driver,
* allowing an application to read the buffer without fear that firmware is
* overwritting information in the buffer.
*/
struct mpt2_diag_release {
struct mpt2_ioctl_header hdr;
uint32_t unique_id;
};
/**
* struct mpt2_diag_read_buffer - request for copy of the diag buffer
* @hdr - generic header
* @status -
* @reserved -
* @flags - misc flags
* @starting_offset - starting offset within drivers buffer where to start
* reading data at into the specified application buffer
* @bytes_to_read - number of bytes to copy from the drivers buffer into the
* application buffer starting at starting_offset.
* @unique_id - unique id associated with this buffer.
* @diagnostic_data - data payload
*/
struct mpt2_diag_read_buffer {
struct mpt2_ioctl_header hdr;
uint8_t status;
uint8_t reserved;
uint16_t flags;
uint32_t starting_offset;
uint32_t bytes_to_read;
uint32_t unique_id;
uint32_t diagnostic_data[1];
};
#endif /* MPT2SAS_CTL_H_INCLUDED */

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/***************************************************************************
* *
* Copyright 2012 LSI Corporation. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Corporation. The *
* receipt of or possession of this file does not convey any rights to *
* reproduce or disclose its contents or to manufacture, use, or sell *
* anything it may describe, in whole, or in part, without the specific *
* written consent of LSI Corporation. *
* *
***************************************************************************
*/
#ifndef MPTCTL_H_INCLUDED
#define MPTCTL_H_INCLUDED
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
#include "linux/version.h"
#include "../lsi/mpi_ioc.h"
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*
*
*/
#define MPT_MISCDEV_BASENAME "mptctl"
#define MPT_MISCDEV_PATHNAME "/dev/" MPT_MISCDEV_BASENAME
#define MPT_CSMI_DESCRIPTION "LSI Logic Corporation: Fusion MPT Driver " MPT_LINUX_VERSION_COMMON
#define MPT_PRODUCT_LENGTH 12
/*
* Generic MPT Control IOCTLs and structures
*/
#define MPT_MAGIC_NUMBER 'm'
#define MPTRWPERF _IOWR(MPT_MAGIC_NUMBER,0,struct mpt_raw_r_w)
#define MPTFWDOWNLOAD _IOWR(MPT_MAGIC_NUMBER,15,struct mpt_fw_xfer)
#define MPTFWDOWNLOADBOOT _IOWR(MPT_MAGIC_NUMBER,16,struct mpt_fw_xfer)
#define MPTCOMMAND _IOWR(MPT_MAGIC_NUMBER,20,struct mpt_ioctl_command)
#if defined(__KERNEL__) && defined(MPT_CONFIG_COMPAT)
#define MPTFWDOWNLOAD32 _IOWR(MPT_MAGIC_NUMBER,15,struct mpt_fw_xfer32)
#define MPTCOMMAND32 _IOWR(MPT_MAGIC_NUMBER,20,struct mpt_ioctl_command32)
#endif
#define MPTIOCINFO _IOWR(MPT_MAGIC_NUMBER,17,struct mpt_ioctl_iocinfo)
#define MPTIOCINFO1 _IOWR(MPT_MAGIC_NUMBER,17,struct mpt_ioctl_iocinfo_rev0)
#define MPTIOCINFO2 _IOWR(MPT_MAGIC_NUMBER,17,struct mpt_ioctl_iocinfo_rev1)
#define MPTTARGETINFO _IOWR(MPT_MAGIC_NUMBER,18,struct mpt_ioctl_targetinfo)
#define MPTTEST _IOWR(MPT_MAGIC_NUMBER,19,struct mpt_ioctl_test)
#define MPTEVENTQUERY _IOWR(MPT_MAGIC_NUMBER,21,struct mpt_ioctl_eventquery)
#define MPTEVENTENABLE _IOWR(MPT_MAGIC_NUMBER,22,struct mpt_ioctl_eventenable)
#define MPTEVENTREPORT _IOWR(MPT_MAGIC_NUMBER,23,struct mpt_ioctl_eventreport)
#define MPTHARDRESET _IOWR(MPT_MAGIC_NUMBER,24,struct mpt_ioctl_diag_reset)
#define MPTFWREPLACE _IOWR(MPT_MAGIC_NUMBER,25,struct mpt_ioctl_replace_fw)
#define MPTDIAGREGISTER _IOWR(MPT_MAGIC_NUMBER,26,mpt_diag_register_t)
#define MPTDIAGRELEASE _IOWR(MPT_MAGIC_NUMBER,27,mpt_diag_release_t)
#define MPTDIAGUNREGISTER _IOWR(MPT_MAGIC_NUMBER,28,mpt_diag_unregister_t)
#define MPTDIAGQUERY _IOWR(MPT_MAGIC_NUMBER,29,mpt_diag_query_t)
#define MPTDIAGREADBUFFER _IOWR(MPT_MAGIC_NUMBER,30,mpt_diag_read_buffer_t)
#define MPTHBAPCIINFO _IOWR(MPT_MAGIC_NUMBER,31,struct mpt_ioctl_hbapciinfo)
#define MPTDIAGRESET _IOWR(MPT_MAGIC_NUMBER,32,struct mpt_ioctl_diag_reset)
/*
* SPARC PLATFORM REMARKS:
* IOCTL data structures that contain pointers
* will have different sizes in the driver and applications
* (as the app. will not use 8-byte pointers).
* Apps should use MPTFWDOWNLOAD and MPTCOMMAND.
* The driver will convert data from
* mpt_fw_xfer32 (mpt_ioctl_command32) to mpt_fw_xfer (mpt_ioctl_command)
* internally.
*
* If data structures change size, must handle as in IOCGETINFO.
*/
struct mpt_fw_xfer {
unsigned int iocnum; /* IOC unit number */
unsigned int fwlen;
void *bufp; /* Pointer to firmware buffer */
};
#if defined(__KERNEL__) && defined(MPT_CONFIG_COMPAT)
struct mpt_fw_xfer32 {
unsigned int iocnum;
unsigned int fwlen;
U32 bufp;
};
#endif /*}*/
/*
* IOCTL header structure.
* iocnum - must be defined.
* port - must be defined for all IOCTL commands other than MPTIOCINFO
* maxDataSize - ignored on MPTCOMMAND commands
* - ignored on MPTFWREPLACE commands
* - on query commands, reports the maximum number of bytes to be returned
* to the host driver (count includes the header).
* That is, set to sizeof(struct mpt_ioctl_iocinfo) for fixed sized commands.
* Set to sizeof(struct mpt_ioctl_targetinfo) + datasize for variable
* sized commands. (MPTTARGETINFO, MPTEVENTREPORT)
*/
typedef struct _mpt_ioctl_header {
unsigned int iocnum; /* IOC unit number */
unsigned int port; /* IOC port number */
int maxDataSize; /* Maximum Num. bytes to transfer on read */
} mpt_ioctl_header;
/*
* Issue a diagnostic reset
*/
struct mpt_ioctl_diag_reset {
mpt_ioctl_header hdr;
};
/*
* PCI bus/device/function information structure.
*/
struct mpt_ioctl_pci_info {
union {
struct {
unsigned int deviceNumber : 5;
unsigned int functionNumber : 3;
unsigned int busNumber : 24;
} bits;
unsigned int asUlong;
} u;
};
struct mpt_ioctl_pci_info2 {
union {
struct {
unsigned int deviceNumber : 5;
unsigned int functionNumber : 3;
unsigned int busNumber : 24;
} bits;
unsigned int asUlong;
} u;
int segmentID;
};
/*
* Adapter Information Page
* Read only.
* Data starts at offset 0xC
*/
#define MPT_IOCTL_INTERFACE_SCSI (0x00)
#define MPT_IOCTL_INTERFACE_FC (0x01)
#define MPT_IOCTL_INTERFACE_SAS (0x03)
#define MPT_IOCTL_VERSION_LENGTH (32)
struct mpt_ioctl_iocinfo {
mpt_ioctl_header hdr;
int adapterType; /* SCSI or FCP */
int port; /* port number */
int pciId; /* PCI Id. */
int hwRev; /* hardware revision */
int subSystemDevice; /* PCI subsystem Device ID */
int subSystemVendor; /* PCI subsystem Vendor ID */
int numDevices; /* number of devices */
int FWVersion; /* FW Version (integer) */
int BIOSVersion; /* BIOS Version (integer) */
char driverVersion[MPT_IOCTL_VERSION_LENGTH]; /* Driver Version (string) */
char busChangeEvent;
char hostId;
char rsvd[2];
struct mpt_ioctl_pci_info2 pciInfo; /* Added Rev 2 */
};
struct mpt_ioctl_iocinfo_rev1 {
mpt_ioctl_header hdr;
int adapterType; /* SCSI or FCP */
int port; /* port number */
int pciId; /* PCI Id. */
int hwRev; /* hardware revision */
int subSystemDevice; /* PCI subsystem Device ID */
int subSystemVendor; /* PCI subsystem Vendor ID */
int numDevices; /* number of devices */
int FWVersion; /* FW Version (integer) */
int BIOSVersion; /* BIOS Version (integer) */
char driverVersion[MPT_IOCTL_VERSION_LENGTH]; /* Driver Version (string) */
char busChangeEvent;
char hostId;
char rsvd[2];
struct mpt_ioctl_pci_info pciInfo; /* Added Rev 1 */
};
/* Original structure, must always accept these
* IOCTLs. 4 byte pads can occur based on arch with
* above structure. Wish to re-align, but cannot.
*/
struct mpt_ioctl_iocinfo_rev0 {
mpt_ioctl_header hdr;
int adapterType; /* SCSI or FCP */
int port; /* port number */
int pciId; /* PCI Id. */
int hwRev; /* hardware revision */
int subSystemDevice; /* PCI subsystem Device ID */
int subSystemVendor; /* PCI subsystem Vendor ID */
int numDevices; /* number of devices */
int FWVersion; /* FW Version (integer) */
int BIOSVersion; /* BIOS Version (integer) */
char driverVersion[MPT_IOCTL_VERSION_LENGTH]; /* Driver Version (string) */
char busChangeEvent;
char hostId;
char rsvd[2];
};
/*
* Device Information Page
* Report the number of, and ids of, all targets
* on this IOC. The ids array is a packed structure
* of the known targetInfo.
* bits 31-24: reserved
* 23-16: LUN
* 15- 8: Bus Number
* 7- 0: Target ID
*/
struct mpt_ioctl_targetinfo {
mpt_ioctl_header hdr;
int numDevices; /* Num targets on this ioc */
int targetInfo[1];
};
/*
* Event reporting IOCTL's. These IOCTL's will
* use the following defines:
*/
struct mpt_ioctl_eventquery {
mpt_ioctl_header hdr;
unsigned short eventEntries;
unsigned short reserved;
unsigned int eventTypes;
};
struct mpt_ioctl_eventenable {
mpt_ioctl_header hdr;
unsigned int eventTypes;
};
#ifndef __KERNEL__
typedef struct {
uint event;
uint eventContext;
uint data[2];
} MPT_IOCTL_EVENTS;
#endif
struct mpt_ioctl_eventreport {
mpt_ioctl_header hdr;
MPT_IOCTL_EVENTS eventData[1];
};
#define MPT_MAX_NAME 32
struct mpt_ioctl_test {
mpt_ioctl_header hdr;
U8 name[MPT_MAX_NAME];
int chip_type;
U8 product [MPT_PRODUCT_LENGTH];
};
/* Replace the FW image cached in host driver memory
* newImageSize - image size in bytes
* newImage - first byte of the new image
*/
typedef struct mpt_ioctl_replace_fw {
mpt_ioctl_header hdr;
int newImageSize;
U8 newImage[1];
} mpt_ioctl_replace_fw_t;
struct mpt_ioctl_mptpciinfo {
U8 iocNumber;
U8 iocState;
U8 revisionID;
U8 reserved1;
U16 vendorID;
U16 deviceID;
U16 subSystemVendorID;
U16 subSystemID;
};
struct mpt_ioctl_hbapciinfo {
mpt_ioctl_header hdr;
U8 totalIOC;
U8 reserved[3];
struct mpt_ioctl_mptpciinfo hbapciinfo[18];
};
/* General MPT Pass through data structure
*
* iocnum
* timeout - in seconds, command timeout. If 0, set by driver to
* default value.
* replyFrameBufPtr - reply location
* dataInBufPtr - destination for read
* dataOutBufPtr - data source for write
* senseDataPtr - sense data location
* maxReplyBytes - maximum number of reply bytes to be sent to app.
* dataInSize - num bytes for data transfer in (read)
* dataOutSize - num bytes for data transfer out (write)
* dataSgeOffset - offset in words from the start of the request message
* to the first SGL
* MF[1];
*
* Remark: Some config pages have bi-directional transfer,
* both a read and a write. The basic structure allows for
* a bidirectional set up. Normal messages will have one or
* both of these buffers NULL.
*/
struct mpt_ioctl_command {
mpt_ioctl_header hdr;
int timeout; /* optional (seconds) */
char *replyFrameBufPtr;
char *dataInBufPtr;
char *dataOutBufPtr;
char *senseDataPtr;
int maxReplyBytes;
int dataInSize;
int dataOutSize;
int maxSenseBytes;
int dataSgeOffset;
char MF[1];
};
/*
* SPARC PLATFORM: See earlier remark.
*/
#if defined(__KERNEL__) && defined(MPT_CONFIG_COMPAT)
struct mpt_ioctl_command32 {
mpt_ioctl_header hdr;
int timeout;
U32 replyFrameBufPtr;
U32 dataInBufPtr;
U32 dataOutBufPtr;
U32 senseDataPtr;
int maxReplyBytes;
int dataInSize;
int dataOutSize;
int maxSenseBytes;
int dataSgeOffset;
char MF[1];
};
#endif /*}*/
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
/*
* HP Specific IOCTL Defines and Structures
*/
#define CPQFCTS_IOC_MAGIC 'Z'
#define HP_IOC_MAGIC 'Z'
#define HP_GETHOSTINFO _IOR(HP_IOC_MAGIC, 20, hp_host_info_t)
#define HP_GETHOSTINFO1 _IOR(HP_IOC_MAGIC, 20, hp_host_info_rev0_t)
#define HP_GETTARGETINFO _IOR(HP_IOC_MAGIC, 21, hp_target_info_t)
/* All HP IOCTLs must include this header
*/
typedef struct _hp_header {
unsigned int iocnum;
unsigned int host;
unsigned int channel;
unsigned int id;
unsigned int lun;
} hp_header_t;
/*
* Header:
* iocnum required (input)
* host ignored
* channe ignored
* id ignored
* lun ignored
*/
typedef struct _hp_host_info {
hp_header_t hdr;
U16 vendor;
U16 device;
U16 subsystem_vendor;
U16 subsystem_id;
U8 devfn;
U8 bus;
ushort host_no; /* SCSI Host number, if scsi driver not loaded*/
U8 fw_version[16]; /* string */
U8 serial_number[24]; /* string */
U32 ioc_status;
U32 bus_phys_width;
U32 base_io_addr;
U32 rsvd;
unsigned int hard_resets; /* driver initiated resets */
unsigned int soft_resets; /* ioc, external resets */
unsigned int timeouts; /* num timeouts */
} hp_host_info_t;
/* replace ulongs with uints, need to preserve backwards
* compatibility.
*/
typedef struct _hp_host_info_rev0 {
hp_header_t hdr;
U16 vendor;
U16 device;
U16 subsystem_vendor;
U16 subsystem_id;
U8 devfn;
U8 bus;
ushort host_no; /* SCSI Host number, if scsi driver not loaded*/
U8 fw_version[16]; /* string */
U8 serial_number[24]; /* string */
U32 ioc_status;
U32 bus_phys_width;
U32 base_io_addr;
U32 rsvd;
unsigned long hard_resets; /* driver initiated resets */
unsigned long soft_resets; /* ioc, external resets */
unsigned long timeouts; /* num timeouts */
} hp_host_info_rev0_t;
/*
* Header:
* iocnum required (input)
* host required
* channel required (bus number)
* id required
* lun ignored
*
* All error values between 0 and 0xFFFF in size.
*/
typedef struct _hp_target_info {
hp_header_t hdr;
U32 parity_errors;
U32 phase_errors;
U32 select_timeouts;
U32 message_rejects;
U32 negotiated_speed;
U8 negotiated_width;
U8 rsvd[7]; /* 8 byte alignment */
} hp_target_info_t;
#define HP_STATUS_OTHER 1
#define HP_STATUS_OK 2
#define HP_STATUS_FAILED 3
#define HP_BUS_WIDTH_UNK 1
#define HP_BUS_WIDTH_8 2
#define HP_BUS_WIDTH_16 3
#define HP_BUS_WIDTH_32 4
#define HP_DEV_SPEED_ASYNC 2
#define HP_DEV_SPEED_FAST 3
#define HP_DEV_SPEED_ULTRA 4
#define HP_DEV_SPEED_ULTRA2 5
#define HP_DEV_SPEED_ULTRA160 6
#define HP_DEV_SPEED_SCSI1 7
#define HP_DEV_SPEED_ULTRA320 8
/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
#define MPI_FW_DIAG_IOCTL (0x80646961) // dia
#define MPI_FW_DIAG_TYPE_REGISTER (0x00000001)
#define MPI_FW_DIAG_TYPE_UNREGISTER (0x00000002)
#define MPI_FW_DIAG_TYPE_QUERY (0x00000003)
#define MPI_FW_DIAG_TYPE_READ_BUFFER (0x00000004)
#define MPI_FW_DIAG_TYPE_RELEASE (0x00000005)
#define MPI_FW_DIAG_INVALID_UID (0x00000000)
#define FW_DIAGNOSTIC_BUFFER_COUNT (3)
#define FW_DIAGNOSTIC_UID_NOT_FOUND (0xFF)
#define MPI_FW_DIAG_ERROR_SUCCESS (0x00000000)
#define MPI_FW_DIAG_ERROR_FAILURE (0x00000001)
#define MPI_FW_DIAG_ERROR_INVALID_PARAMETER (0x00000002)
#define MPI_FW_DIAG_ERROR_POST_FAILED (0x00000010)
#define MPI_FW_DIAG_ERROR_INVALID_UID (0x00000011)
#define MPI_FW_DIAG_ERROR_RELEASE_FAILED (0x00000012)
#define MPI_FW_DIAG_ERROR_NO_BUFFER (0x00000013)
#define MPI_FW_DIAG_ERROR_ALREADY_RELEASED (0x00000014)
#define MPT_DIAG_CAPABILITY(bufftype) (MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER << bufftype)
typedef struct _MPI_FW_DIAG_REGISTER
{
U8 TraceLevel;
U8 BufferType;
U16 Flags;
U32 ExtendedType;
U32 ProductSpecific[4];
U32 RequestedBufferSize;
U32 UniqueId;
} MPI_FW_DIAG_REGISTER, *PTR_MPI_FW_DIAG_REGISTER;
typedef struct _mpt_diag_register {
mpt_ioctl_header hdr;
MPI_FW_DIAG_REGISTER data;
} mpt_diag_register_t;
typedef struct _MPI_FW_DIAG_UNREGISTER
{
U32 UniqueId;
} MPI_FW_DIAG_UNREGISTER, *PTR_MPI_FW_DIAG_UNREGISTER;
typedef struct _mpt_diag_unregister {
mpt_ioctl_header hdr;
MPI_FW_DIAG_UNREGISTER data;
} mpt_diag_unregister_t;
#define MPI_FW_DIAG_FLAG_APP_OWNED (0x0001)
#define MPI_FW_DIAG_FLAG_BUFFER_VALID (0x0002)
#define MPI_FW_DIAG_FLAG_FW_BUFFER_ACCESS (0x0004)
typedef struct _MPI_FW_DIAG_QUERY
{
U8 TraceLevel;
U8 BufferType;
U16 Flags;
U32 ExtendedType;
U32 ProductSpecific[4];
U32 DataSize;
U32 DriverAddedBufferSize;
U32 UniqueId;
} MPI_FW_DIAG_QUERY, *PTR_MPI_FW_DIAG_QUERY;
typedef struct _mpt_diag_query {
mpt_ioctl_header hdr;
MPI_FW_DIAG_QUERY data;
} mpt_diag_query_t;
typedef struct _MPI_FW_DIAG_RELEASE
{
U32 UniqueId;
} MPI_FW_DIAG_RELEASE, *PTR_MPI_FW_DIAG_RELEASE;
typedef struct _mpt_diag_release {
mpt_ioctl_header hdr;
MPI_FW_DIAG_RELEASE data;
} mpt_diag_release_t;
#define MPI_FW_DIAG_FLAG_REREGISTER (0x0001)
typedef struct _MPI_FW_DIAG_READ_BUFFER
{
U8 Status;
U8 Reserved;
U16 Flags;
U32 StartingOffset;
U32 BytesToRead;
U32 UniqueId;
U32 DiagnosticData[1];
} MPI_FW_DIAG_READ_BUFFER, *PTR_MPI_FW_DIAG_READ_BUFFER;
typedef struct _mpt_diag_read_buffer {
mpt_ioctl_header hdr;
MPI_FW_DIAG_READ_BUFFER data;
} mpt_diag_read_buffer_t;
typedef struct _mpt_FWDownload_MF {
FWDownload_t FWMessage;
U32 SGL_Word;
} mpt_FWDownload_MF_t;
#endif

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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright 1998 LSI Logic Corporation. All rights reserved.
*
* This file is confidential and a trade secret of LSI Logic. The
* receipt of or possession of this file does not convey any rights to
* reproduce or disclose its contents or to manufacture, use, or sell
* anything it may describe, in whole, or in part, without the specific
* written consent of LSI Logic Corporation.
*/
#ifndef _MPTSAS_IOCTL_H
#define _MPTSAS_IOCTL_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/types.h>
#define MPTIOCTL ('I' << 8)
#define MPTIOCTL_GET_ADAPTER_DATA (MPTIOCTL | 1)
#define MPTIOCTL_UPDATE_FLASH (MPTIOCTL | 2)
#define MPTIOCTL_RESET_ADAPTER (MPTIOCTL | 3)
#define MPTIOCTL_PASS_THRU (MPTIOCTL | 4)
#define MPTIOCTL_EVENT_QUERY (MPTIOCTL | 5)
#define MPTIOCTL_EVENT_ENABLE (MPTIOCTL | 6)
#define MPTIOCTL_EVENT_REPORT (MPTIOCTL | 7)
#define MPTIOCTL_GET_PCI_INFO (MPTIOCTL | 8)
#define MPTIOCTL_DIAG_ACTION (MPTIOCTL | 9)
/*
* The following are our ioctl() return status values. If everything went
* well, we return good status. If the buffer length sent to us is too short
* we return a status to tell the user.
*/
#define MPTIOCTL_STATUS_GOOD 0
#define MPTIOCTL_STATUS_LEN_TOO_SHORT 1
/*
* The following is the MPTIOCTL_GET_ADAPTER_DATA data structure. This data
* structure is setup so that we hopefully are properly aligned for both
* 32-bit and 64-bit mode applications.
*
* Adapter Type - Value = 4 = SCSI Protocol through SAS-2 adapter
*
* MPI Port Number - The PCI Function number for this device
*
* PCI Device HW Id - The PCI device number for this device
*
*/
#define MPTIOCTL_ADAPTER_TYPE_SAS2 4
typedef struct mptsas_adapter_data
{
uint32_t StructureLength;
uint32_t AdapterType;
uint32_t MpiPortNumber;
uint32_t PCIDeviceHwId;
uint32_t PCIDeviceHwRev;
uint32_t SubSystemId;
uint32_t SubsystemVendorId;
uint32_t Reserved1;
uint32_t MpiFirmwareVersion;
uint32_t BiosVersion;
uint8_t DriverVersion[32];
uint8_t Reserved2;
uint8_t ScsiId;
uint16_t Reserved3;
uint32_t PciInformation;
uint32_t PciSegmentId;
} mptsas_adapter_data_t;
typedef struct mptsas_update_flash
{
uint64_t PtrBuffer;
uint32_t ImageChecksum;
uint32_t ImageOffset;
uint32_t ImageSize;
uint32_t ImageType;
} mptsas_update_flash_t;
#define MPTSAS_PASS_THRU_DIRECTION_NONE 0
#define MPTSAS_PASS_THRU_DIRECTION_READ 1
#define MPTSAS_PASS_THRU_DIRECTION_WRITE 2
#define MPTSAS_PASS_THRU_DIRECTION_BOTH 3
typedef struct mptsas_pass_thru
{
uint64_t PtrRequest;
uint64_t PtrReply;
uint64_t PtrData;
uint32_t RequestSize;
uint32_t ReplySize;
uint32_t DataSize;
uint32_t DataDirection;
uint64_t PtrDataOut;
uint32_t DataOutSize;
uint32_t Timeout;
} mptsas_pass_thru_t;
/*
* Event queue defines
*/
#define MPTSAS_EVENT_QUEUE_SIZE (50) /* Max Events stored in driver */
#define MPTSAS_MAX_EVENT_DATA_LENGTH (48) /* Size of each event in Dwords */
typedef struct mptsas_event_query
{
uint16_t Entries;
uint16_t Reserved;
uint32_t Types[4];
} mptsas_event_query_t;
typedef struct mptsas_event_enable
{
uint32_t Types[4];
} mptsas_event_enable_t;
/*
* Event record entry for ioctl.
*/
typedef struct mptsas_event_entry
{
uint32_t Type;
uint32_t Number;
uint32_t Data[MPTSAS_MAX_EVENT_DATA_LENGTH];
} mptsas_event_entry_t;
typedef struct mptsas_event_report
{
uint32_t Size;
mptsas_event_entry_t Events[1];
} mptsas_event_report_t;
typedef struct mptsas_pci_info
{
uint32_t BusNumber;
uint8_t DeviceNumber;
uint8_t FunctionNumber;
uint16_t InterruptVector;
uint8_t PciHeader[256];
} mptsas_pci_info_t;
typedef struct mptsas_diag_action
{
uint32_t Action;
uint32_t Length;
uint64_t PtrDiagAction;
uint32_t ReturnCode;
} mptsas_diag_action_t;
#define MPTSAS_FW_DIAGNOSTIC_BUFFER_COUNT (3)
#define MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND (0xFF)
#define MPTSAS_FW_DIAG_NEW (0x806E6577)
#define MPTSAS_FW_DIAG_TYPE_REGISTER (0x00000001)
#define MPTSAS_FW_DIAG_TYPE_UNREGISTER (0x00000002)
#define MPTSAS_FW_DIAG_TYPE_QUERY (0x00000003)
#define MPTSAS_FW_DIAG_TYPE_READ_BUFFER (0x00000004)
#define MPTSAS_FW_DIAG_TYPE_RELEASE (0x00000005)
#define MPTSAS_FW_DIAG_INVALID_UID (0x00000000)
#define MPTSAS_FW_DIAG_ERROR_SUCCESS (0x00000000)
#define MPTSAS_FW_DIAG_ERROR_FAILURE (0x00000001)
#define MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER (0x00000002)
#define MPTSAS_FW_DIAG_ERROR_POST_FAILED (0x00000010)
#define MPTSAS_FW_DIAG_ERROR_INVALID_UID (0x00000011)
#define MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED (0x00000012)
#define MPTSAS_FW_DIAG_ERROR_NO_BUFFER (0x00000013)
#define MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED (0x00000014)
typedef struct mptsas_fw_diag_register
{
uint8_t Reserved1;
uint8_t BufferType;
uint16_t ApplicationFlags;
uint32_t DiagnosticFlags;
uint32_t ProductSpecific[23];
uint32_t RequestedBufferSize;
uint32_t UniqueId;
} mptsas_fw_diag_register_t;
typedef struct mptsas_fw_diag_unregister
{
uint32_t UniqueId;
} mptsas_fw_diag_unregister_t;
#define MPTSAS_FW_DIAG_FLAG_APP_OWNED (0x0001)
#define MPTSAS_FW_DIAG_FLAG_BUFFER_VALID (0x0002)
#define MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS (0x0004)
typedef struct mptsas_fw_diag_query
{
uint8_t Reserved1;
uint8_t BufferType;
uint16_t ApplicationFlags;
uint32_t DiagnosticFlags;
uint32_t ProductSpecific[23];
uint32_t TotalBufferSize;
uint32_t DriverAddedBufferSize;
uint32_t UniqueId;
} mptsas_fw_diag_query_t;
typedef struct mptsas_fw_diag_release
{
uint32_t UniqueId;
} mptsas_fw_diag_release;
#define MPTSAS_FW_DIAG_FLAG_REREGISTER (0x0001)
#define MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE (0x0002)
typedef struct mptsas_diag_read_buffer
{
uint8_t Status;
uint8_t Reserved;
uint16_t Flags;
uint32_t StartingOffset;
uint32_t BytesToRead;
uint32_t UniqueId;
uint32_t DataBuffer[1];
} mptsas_diag_read_buffer_t;
#ifdef __cplusplus
}
#endif
#endif /* _MPTSAS_IOCTL_H */

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/*++ BUILD Version: 0001 // Increment this if a change has global effects
Copyright (c) 1990-1999 Microsoft Corporation
Module Name:
ntddscsi.h
Abstract:
This is the include file that defines all constants and types for
accessing the SCSI port adapters.
Author:
Jeff Havens
Revision History:
--*/
//
// Interface GUIDs
//
// need these GUIDs outside conditional includes so that user can
// #include <ntddscsi.h> in precompiled header
// #include <initguid.h> in a single source file
// #include <ntddscsi.h> in that source file a second time to instantiate the GUIDs
//
#ifdef DEFINE_GUID
//
// Make sure FAR is defined...
//
#ifndef FAR
#ifdef _WIN32
#define FAR
#else
#define FAR _far
#endif
#endif
DEFINE_GUID(ScsiRawInterfaceGuid, 0x53f56309L, 0xb6bf, 0x11d0, 0x94, 0xf2, 0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
DEFINE_GUID(WmiScsiAddressGuid, 0x53f5630fL, 0xb6bf, 0x11d0, 0x94, 0xf2, 0x00, 0xa0, 0xc9, 0x1e, 0xfb, 0x8b);
#endif
#ifndef _NTDDSCSIH_
#define _NTDDSCSIH_
#ifdef __cplusplus
extern "C" {
#endif
//
// Device Name - this string is the name of the device. It is the name
// that should be passed to NtOpenFile when accessing the device.
//
// Note: For devices that support multiple units, it should be suffixed
// with the Ascii representation of the unit number.
//
#define IOCTL_SCSI_BASE FILE_DEVICE_CONTROLLER
#define DD_SCSI_DEVICE_NAME "\\Device\\ScsiPort"
//
// NtDeviceIoControlFile IoControlCode values for this device.
//
// Warning: Remember that the low two bits of the code specify how the
// buffers are passed to the driver!
//
#define IOCTL_SCSI_PASS_THROUGH CTL_CODE(IOCTL_SCSI_BASE, 0x0401, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS)
#define IOCTL_SCSI_MINIPORT CTL_CODE(IOCTL_SCSI_BASE, 0x0402, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS)
#define IOCTL_SCSI_GET_INQUIRY_DATA CTL_CODE(IOCTL_SCSI_BASE, 0x0403, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_SCSI_GET_CAPABILITIES CTL_CODE(IOCTL_SCSI_BASE, 0x0404, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_SCSI_PASS_THROUGH_DIRECT CTL_CODE(IOCTL_SCSI_BASE, 0x0405, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS)
#define IOCTL_SCSI_GET_ADDRESS CTL_CODE(IOCTL_SCSI_BASE, 0x0406, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_SCSI_RESCAN_BUS CTL_CODE(IOCTL_SCSI_BASE, 0x0407, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_SCSI_GET_DUMP_POINTERS CTL_CODE(IOCTL_SCSI_BASE, 0x0408, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_SCSI_FREE_DUMP_POINTERS CTL_CODE(IOCTL_SCSI_BASE, 0x0409, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_IDE_PASS_THROUGH CTL_CODE(IOCTL_SCSI_BASE, 0x040a, METHOD_BUFFERED, FILE_READ_ACCESS | FILE_WRITE_ACCESS)
//
// Define the SCSI pass through structure.
//
typedef struct _SCSI_PASS_THROUGH {
USHORT Length;
UCHAR ScsiStatus;
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
UCHAR CdbLength;
UCHAR SenseInfoLength;
UCHAR DataIn;
ULONG DataTransferLength;
ULONG TimeOutValue;
ULONG_PTR DataBufferOffset;
ULONG SenseInfoOffset;
UCHAR Cdb[16];
}SCSI_PASS_THROUGH, *PSCSI_PASS_THROUGH;
//
// Define the SCSI pass through direct structure.
//
typedef struct _SCSI_PASS_THROUGH_DIRECT {
USHORT Length;
UCHAR ScsiStatus;
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
UCHAR CdbLength;
UCHAR SenseInfoLength;
UCHAR DataIn;
ULONG DataTransferLength;
ULONG TimeOutValue;
PVOID DataBuffer;
ULONG SenseInfoOffset;
UCHAR Cdb[16];
}SCSI_PASS_THROUGH_DIRECT, *PSCSI_PASS_THROUGH_DIRECT;
//
// Define the SCSI pass through direct structure for Win64 (thunking).
//
#if defined(_WIN64)
typedef struct _SCSI_PASS_THROUGH32 {
USHORT Length;
UCHAR ScsiStatus;
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
UCHAR CdbLength;
UCHAR SenseInfoLength;
UCHAR DataIn;
ULONG DataTransferLength;
ULONG TimeOutValue;
ULONG32 DataBufferOffset;
ULONG SenseInfoOffset;
UCHAR Cdb[16];
}SCSI_PASS_THROUGH32, *PSCSI_PASS_THROUGH32;
//
// Define the SCSI pass through direct structure.
//
typedef struct _SCSI_PASS_THROUGH_DIRECT32 {
USHORT Length;
UCHAR ScsiStatus;
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
UCHAR CdbLength;
UCHAR SenseInfoLength;
UCHAR DataIn;
ULONG DataTransferLength;
ULONG TimeOutValue;
VOID * POINTER_32 DataBuffer;
ULONG SenseInfoOffset;
UCHAR Cdb[16];
}SCSI_PASS_THROUGH_DIRECT32, *PSCSI_PASS_THROUGH_DIRECT32;
#endif
//
// Define SCSI information.
// Used with the IOCTL_SCSI_GET_INQUIRY_DATA IOCTL.
//
typedef struct _SCSI_BUS_DATA {
UCHAR NumberOfLogicalUnits;
UCHAR InitiatorBusId;
ULONG InquiryDataOffset;
}SCSI_BUS_DATA, *PSCSI_BUS_DATA;
//
// Define SCSI adapter bus information structure..
// Used with the IOCTL_SCSI_GET_INQUIRY_DATA IOCTL.
//
typedef struct _SCSI_ADAPTER_BUS_INFO {
UCHAR NumberOfBuses;
SCSI_BUS_DATA BusData[1];
} SCSI_ADAPTER_BUS_INFO, *PSCSI_ADAPTER_BUS_INFO;
//
// Define SCSI adapter bus information.
// Used with the IOCTL_SCSI_GET_INQUIRY_DATA IOCTL.
//
typedef struct _SCSI_INQUIRY_DATA {
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
BOOLEAN DeviceClaimed;
ULONG InquiryDataLength;
ULONG NextInquiryDataOffset;
UCHAR InquiryData[1];
}SCSI_INQUIRY_DATA, *PSCSI_INQUIRY_DATA;
//
// Define header for I/O control SRB.
//
typedef struct _SRB_IO_CONTROL {
ULONG HeaderLength;
UCHAR Signature[8];
ULONG Timeout;
ULONG ControlCode;
ULONG ReturnCode;
ULONG Length;
} SRB_IO_CONTROL, *PSRB_IO_CONTROL;
//
// SCSI port driver capabilities structure.
//
typedef struct _IO_SCSI_CAPABILITIES {
//
// Length of this structure
//
ULONG Length;
//
// Maximum transfer size in single SRB
//
ULONG MaximumTransferLength;
//
// Maximum number of physical pages per data buffer
//
ULONG MaximumPhysicalPages;
//
// Async calls from port to class
//
ULONG SupportedAsynchronousEvents;
//
// Alignment mask for data transfers.
//
ULONG AlignmentMask;
//
// Supports tagged queuing
//
BOOLEAN TaggedQueuing;
//
// Host adapter scans down for bios devices.
//
BOOLEAN AdapterScansDown;
//
// The host adapter uses programmed I/O.
//
BOOLEAN AdapterUsesPio;
} IO_SCSI_CAPABILITIES, *PIO_SCSI_CAPABILITIES;
typedef struct _SCSI_ADDRESS {
ULONG Length;
UCHAR PortNumber;
UCHAR PathId;
UCHAR TargetId;
UCHAR Lun;
}SCSI_ADDRESS, *PSCSI_ADDRESS;
//
// Define structure for returning crash dump pointers.
//
struct _ADAPTER_OBJECT;
typedef struct _DUMP_POINTERS {
struct _ADAPTER_OBJECT *AdapterObject;
PVOID MappedRegisterBase;
PVOID DumpData;
PVOID CommonBufferVa;
LARGE_INTEGER CommonBufferPa;
ULONG CommonBufferSize;
BOOLEAN AllocateCommonBuffers;
BOOLEAN UseDiskDump;
UCHAR Spare1[2];
PVOID DeviceObject;
} DUMP_POINTERS, *PDUMP_POINTERS;
//
// Define values for pass-through DataIn field.
//
#define SCSI_IOCTL_DATA_OUT 0
#define SCSI_IOCTL_DATA_IN 1
#define SCSI_IOCTL_DATA_UNSPECIFIED 2
#ifdef __cplusplus
}
#endif
#endif

1886
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/* FILE: sym_dmi.h - MPT/Fusion Driver IOCTL Support header file
*
*************************************************************************
* *
* Copyright 2001 LSI Logic. All rights reserved. *
* *
* This file is confidential and a trade secret of LSI Logic. *
* The receipt of or possession of this file does not convey any *
* rights to reproduce or disclose its contents or to manufacture, *
* use, or sell anything is may describe, in whole, or in part, *
* without the specific written consent of LSI Logic. *
* *
************************************************************************/
/*+++HDR
*
* Version History
* ---------------
*
* Date Who? Description
* -------- ---- -------------------------------------------------------
* 03/20/00 SAM Initial version
* 02/14/01 SCH Added Domain Validation
* 05/14/01 SCH Added MPI Event logging
* 07/09/01 SCH Changed MAX_VERSION_STRING from 80 to 32
* 01/02/02 SCH Added MPI diagnostic reset IOCTL
* 10/30/03 SCH Added InBand IOCTL support
* 03/24/04 BJH Added Diagnostic IOCTL support
* 09/10/08 SCH Added ADAPTER_TYPE_SAS2 define
* 10/20/08 SCH Modified diag buffer structures for Gen2
---*/
#ifndef SYM_DMI_H
#define SYM_DMI_H
#define VERSION_SIZE 4
#define MAX_VERSION_STRING 32
// support for MPI messages via an application or service IOCTL
#define MPI_MSG_IOCTL 0x806D7069 // mpi
#define DATA_FROM_APP 0x01
#define SCSI_IO 0x4000
#define DUAL_SGLS 0x8000
typedef struct _IOCTL_DETAILS {
U16 Dir; // data xfer direction
U16 MsgSize; // size in 32 bit words
U32 DataSize; // data xfer size in bytes
U32 FormattedMsg[1];
} IOCTL_DETAILS, *pIOCTL_DETAILS;
// support for host driver info / MPI event logging IOCTL
#define DRVR_INFO_IOCTL 0x8043494D // CIM
/* Adapter Types */
#define ADAPTER_TYPE_SCSI 0
#define ADAPTER_TYPE_SCSI_OVER_FC 1
#define ADAPTER_TYPE_IP_OVER_FC 2
#define ADAPTER_TYPE_SAS 3
#define ADAPTER_TYPE_SAS2 4
/* Page Codes */
#define ADAPTER_INFO_PAGE 1
#define PCI_CONFIG_SPACE_PAGE 3
#define EVENT_QUERY 10
#define EVENT_ENABLE 11
#define GET_EVENTS 12
/* Event Queue Defines */
#define EVENT_QUEUE_SIZE 50
#define MAX_EVENT_DATA_LENGTH 48
// structure to hold PCI bus/device/function information
typedef struct _MPI_PCI_INFO {
union {
struct {
ULONG DeviceNumber:5;
ULONG FunctionNumber:3;
ULONG BusNumber:24;
} bits;
ULONG AsULONG;
} u;
} MPI_PCI_INFO, *PMPI_PCI_INFO;
// Adapter Info structure
typedef struct _DRVR_ADAPTER_INFO_OUT
{
int AdapterType;
int MpiPortNumber;
int PciDeviceId;
int PciDeviceHwRev;
int SubSystem;
int SubSystemVendorId;
int NumDevicesAttached;
int MpiVersion;
U32 BiosVersion;
char DriverVersion[MAX_VERSION_STRING];
BOOLEAN BusChangeEvent;
U8 HostId;
U16 Reserved1;
MPI_PCI_INFO PciInfo;
U32 PciSegmentId;
} DRVR_ADAPTER_INFO_OUT, *PTR_DRVR_ADAPTER_INFO_OUT;
typedef struct _DRVR_INFO_SRB
{
SRB_IO_CONTROL Sic;
int PageCode; // [IN]
char PageVersion[VERSION_SIZE]; // [OUT]
DRVR_ADAPTER_INFO_OUT AdapterPageOut;
} DRVR_INFO_SRB, *PTR_DRVR_INFO_SRB;
typedef struct _PCI_CONFIG_SPACE_SRB
{
SRB_IO_CONTROL Sic;
int PageCode; // [IN]
char PageVersion[VERSION_SIZE]; // [OUT]
U32 reserved[3];
U8 PciConfigSpace[256];
} PCI_CONFIG_SPACE_SRB, *PTR_PCI_CONFIG_SPACE_SRB;
// support for MPI Event Queue
typedef struct _MPI_EVENTS_SRB
{
SRB_IO_CONTROL Sic;
int PageCode; // [IN]
char PageVersion[VERSION_SIZE]; // [OUT]
U32 EventData[1]; // page code dependent
} MPI_EVENTS_SRB, *PTR_MPI_EVENTS_SRB;
typedef struct _MPI_EVENTS_QUEUE
{
U32 EventType; // from reply frame
U32 EventNumber; // from DevExt->EventNum
U32 EventData[MAX_EVENT_DATA_LENGTH]; // from reply frame
} MPI_EVENTS_QUEUE, *PTR_MPI_EVENTS_QUEUE;
// support for MPI Diagnostic Reset IOCTL
#define MPI_DIAG_RESET 0x80727374 // rst
typedef struct _MPI_DIAG_RESET_SRB
{
SRB_IO_CONTROL Sic;
U32 NewImageSize; // replacement image size
U32 NewFWImage[1]; // new FW image to save
} MPI_DIAG_RESET_SRB, *PTR_MPI_DIAG_RESET_SRB;
// A NewImageSize of 0 indicates that no new FW image is being downloaded
// MPI register reae/write access IOCTL
#define MPI_REG_ACCESS 0x80771959 // magic number
#define REG_IO_READ 1
#define REG_IO_WRITE 2
#define REG_MEM_READ 3
#define REG_MEM_WRITE 4
typedef struct _MPI_REG_ACCESS_SRB
{
SRB_IO_CONTROL Sic;
U32 Command; // command (read/write)
U32 RegOffset; // register offset
U32 RegData; // register data
} MPI_REG_ACCESS_SRB, *PTR_MPI_REG_ACCESS_SRB;
// support for bus/target - DevHandle mapping IOCTL
// application can suppy bus/target and get devHandle or
// supply devHandle and get bus/target
#define MPI_BTDH_MAPPING 0x804D4150 // MAP
typedef struct _MPI_BTDH_MAP_SRB
{
SRB_IO_CONTROL Sic;
U32 TargetID; // target ID
U32 Bus; // bus
U16 DevHandle; // device handle
U16 Reserved;
} MPI_BTDH_MAP_SRB, *PTR_MPI_BTDH_MAP_SRB;
#define MPI_FW_DIAG_IOCTL (0x80646961) // dia
#define MPI_FW_DIAG_NEW (0x806E6577) // new
#define MPI_FW_DIAG_TYPE_REGISTER (0x00000001)
#define MPI_FW_DIAG_TYPE_UNREGISTER (0x00000002)
#define MPI_FW_DIAG_TYPE_QUERY (0x00000003)
#define MPI_FW_DIAG_TYPE_READ_BUFFER (0x00000004)
#define MPI_FW_DIAG_TYPE_RELEASE (0x00000005)
#define MPI_FW_DIAG_INVALID_UID (0x00000000)
#define FW_DIAGNOSTIC_BUFFER_COUNT (3)
#define FW_DIAGNOSTIC_UID_NOT_FOUND (0xFF)
#define MPI_FW_DIAG_ERROR_SUCCESS (0x00000000)
#define MPI_FW_DIAG_ERROR_FAILURE (0x00000001)
#define MPI_FW_DIAG_ERROR_INVALID_PARAMETER (0x00000003)
#define MPI_FW_DIAG_ERROR_POST_FAILED (0x00000010)
#define MPI_FW_DIAG_ERROR_INVALID_UID (0x00000011)
#define MPI_FW_DIAG_ERROR_RELEASE_FAILED (0x00000012)
#define MPI_FW_DIAG_ERROR_NO_BUFFER (0x00000013)
#define MPI_FW_DIAG_ERROR_ALREADY_RELEASED (0x00000014)
typedef struct _MPI_FW_DIAG_IOCTL_SRB
{
SRB_IO_CONTROL Sic;
U32 MpiDiagType;
U8 PageVersion[4];
U32 MpiDiagData[1];
} MPI_FW_DIAG_IOCTL_SRB, *PTR_MPI_FW_DIAG_IOCTL_SRB;
/* diag register for gen 1 */
typedef struct _MPI_FW_DIAG_REGISTER
{
U8 TraceLevel;
U8 BufferType;
U16 Flags;
U32 ExtendedType;
U32 ProductSpecific[4];
U32 RequestedBufferSize;
U32 UniqueId;
} MPI_FW_DIAG_REGISTER, *PTR_MPI_FW_DIAG_REGISTER;
typedef struct _MPI_FW_DIAG_UNREGISTER
{
U32 UniqueId;
} MPI_FW_DIAG_UNREGISTER, *PTR_MPI_FW_DIAG_UNREGISTER;
#define MPI_FW_DIAG_FLAG_APP_OWNED (0x0001)
#define MPI_FW_DIAG_FLAG_BUFFER_VALID (0x0002)
#define MPI_FW_DIAG_FLAG_FW_BUFFER_ACCESS (0x0004)
/* diag query for gen 1 */
typedef struct _MPI_FW_DIAG_QUERY
{
U8 TraceLevel;
U8 BufferType;
U16 Flags;
U32 ExtendedType;
U32 ProductSpecific[4];
U32 TotalBufferSize;
U32 DriverAddedBufferSize;
U32 UniqueId;
} MPI_FW_DIAG_QUERY, *PTR_MPI_FW_DIAG_QUERY;
typedef struct _MPI_FW_DIAG_RELEASE
{
U32 UniqueId;
} MPI_FW_DIAG_RELEASE, *PTR_MPI_FW_DIAG_RELEASE;
#define MPI_FW_DIAG_FLAG_REREGISTER (0x0001)
#define MPI_FW_DIAG_FLAG_FORCE_RELEASE (0x0002)
typedef struct _MPI_FW_DIAG_READ_BUFFER
{
U8 Status;
U8 Reserved;
U16 Flags;
U32 StartingOffset;
U32 BytesToRead;
U32 UniqueId;
U32 DataBuffer[1];
} MPI_FW_DIAG_READ_BUFFER, *PTR_MPI_FW_DIAG_READ_BUFFER;
#endif