958 lines
26 KiB
C
958 lines
26 KiB
C
/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <errno.h>
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#include <stdint.h>
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#include <string.h>
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#include "dosemu_debug.h"
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#include "emu.h"
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#include "pic.h"
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#include "port.h"
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#include "libpacket.h"
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#include "ne2000.h"
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#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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#define EN1_PHYS 0x11
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#define EN1_CURPAG 0x17
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#define EN1_MULT 0x18
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
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#define EN3_CONFIG0 0x33
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#define EN3_CONFIG1 0x34
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#define EN3_CONFIG2 0x35
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#define EN3_CONFIG3 0x36
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicast address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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#define NE2000_IRQ 10
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#define NE2000_IOBASE 0x300
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#define NE2000_PMEM_SIZE (32 * 1024)
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#define NE2000_PMEM_START (16 * 1024)
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#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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#define NE2000_MEM_SIZE NE2000_PMEM_END
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#define le16_to_cpu(x) x
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#define le32_to_cpupu(x) *x
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#define cpu_to_le16(x) x
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#define cpu_to_le32wu(p,v) *p = v;
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#define NE2000_EADDR0 0x00 /* hard coded address */
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#define NE2000_EADDR1 0x00 /* this will need to be configurable */
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#define NE2000_EADDR2 0x01
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#define NE2000_EADDR3 0x61
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#define NE2000_EADDR4 0x60
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#define NE2000_EADDR5 0x59
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typedef struct NE2000State {
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uint8_t cmd;
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uint32_t start;
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uint32_t stop;
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uint8_t boundary;
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uint8_t tsr;
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uint8_t tpsr;
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uint16_t tcnt;
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uint16_t rcnt;
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uint32_t rsar;
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uint8_t rsr;
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uint8_t rxcr;
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uint8_t isr;
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uint8_t dcfg;
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uint8_t imr;
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uint8_t phys[6]; /* mac address */
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uint8_t curpag;
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uint8_t mult[8]; /* multicast mask array */
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uint8_t mem[NE2000_MEM_SIZE];
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int fdnet;
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unsigned long irq;
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} NE2000State;
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// Just one instance
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static NE2000State ne2000state;
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// For io_device
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Bit16u ne2000_io_read16(ioport_t port);
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void ne2000_io_write16(ioport_t port, Bit16u value);
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Bit8u ne2000_io_read8(ioport_t port);
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void ne2000_io_write8(ioport_t port, Bit8u value);
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static void ne2000_irq_activate(int);
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static void ne2000_receive_req_async(void *arg);
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static size_t ne2000_receive(NE2000State *s, const uint8_t *buf, size_t size_);
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#ifdef DEBUG_NE2000
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static void N_printhdr(uint8_t *buf);
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#endif
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static void init_cbk(int fd, int mode)
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{
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ne2000state.fdnet = fd;
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}
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void ne2000_priv_init(void)
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{
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if (!config.ne2k)
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return;
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LibpacketInit();
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}
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void ne2000_init(void)
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{
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NE2000State *s = &ne2000state;
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emu_iodev_t io_device;
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s->fdnet = -1;
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if (!config.ne2k)
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return;
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N_printf("NE2000: ne2000_init()\n");
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if (OpenNetworkLink(init_cbk) < 0) {
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N_printf("NE2000: failed to open network device\n");
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return;
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}
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// Setup the IO device within Dosemu
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/* NE2000 Emulation */
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io_device.read_portb = ne2000_io_read8;
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io_device.write_portb = ne2000_io_write8;
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io_device.read_portw = ne2000_io_read16;
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io_device.write_portw = ne2000_io_write16;
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io_device.read_portd = NULL;
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io_device.write_portd = NULL;
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io_device.handler_name = "NE2000 Emulation";
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io_device.start_addr = /* config.ne2000_base */ NE2000_IOBASE;
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io_device.end_addr = /* config.ne2000_base */ NE2000_IOBASE + 0x1f;
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io_device.irq = /* config.ne2000_irq */ NE2000_IRQ;
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io_device.fd = -1;
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if (port_register_handler(io_device, 0) != 0) {
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N_printf("NE2000: Error registering NE2000 port handler\n");
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ne2000_done();
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return;
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}
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/* init control defaults */
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s->irq = pic_irq_list[NE2000_IRQ];
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/* We let DOSEMU handle the interrupt */
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pic_seti(s->irq, NULL, 0, NULL);
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/* Connect up the receiver */
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add_to_io_select(s->fdnet, ne2000_receive_req_async, NULL);
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N_printf("NE2000: Initialisation - Base 0x%03x, IRQ %d\n", NE2000_IOBASE, NE2000_IRQ);
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}
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static void _ne2000_reset(NE2000State *s)
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{
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int i;
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if (s->fdnet < 0) { // Not initialised
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return;
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}
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N_printf("NE2000: ne2000_reset()\n");
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s->isr = ENISR_RESET;
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s->mem[0] = NE2000_EADDR0;
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s->mem[1] = NE2000_EADDR1;
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s->mem[2] = NE2000_EADDR2;
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s->mem[3] = NE2000_EADDR3;
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s->mem[4] = NE2000_EADDR4;
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s->mem[5] = NE2000_EADDR5;
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// try to get the MAC address from the device and just copy the card id
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GetDeviceHardwareAddress(s->mem);
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N_printf("NE2000: HWADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
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s->mem[0], s->mem[1], s->mem[2], s->mem[3], s->mem[4], s->mem[5]);
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s->mem[14] = 0x57;
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s->mem[15] = 0x57;
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) {
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i];
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}
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}
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void ne2000_reset(void)
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{
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_ne2000_reset(&ne2000state);
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}
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void ne2000_done(void)
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{
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NE2000State *s = &ne2000state;
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if (s->fdnet < 0) { // Not initialised
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return;
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}
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N_printf("NE2000: ne2000_done()\n");
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close(s->fdnet);
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s->fdnet = -1;
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}
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static void ne2000_ether_send(NE2000State *s, uint8_t *buf, int len)
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{
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int slen;
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#ifdef DEBUG_NE2000
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N_printf("NE2000: ne2000_ether_send(%p, %d)\n", buf, len);
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N_printhdr(buf);
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#endif
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slen = write(s->fdnet, buf, len);
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if (slen < 0)
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N_printf("NE2000: write() call failed: %s\n", strerror(errno));
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else if (slen < len)
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N_printf("NE2000: write() call underrun: %d/%d\n", slen, len);
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}
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static int ne2000_ether_recv(NE2000State *s, uint8_t *buf, int bufsiz)
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{
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struct timeval tv;
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fd_set readset;
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int ret;
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tv.tv_sec = 0;
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tv.tv_usec = 0;
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/* anything ready? */
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FD_ZERO(&readset);
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FD_SET(s->fdnet, &readset);
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/* anything ready? */
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if (select(s->fdnet + 1, &readset, NULL, NULL, &tv) <= 0) {
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N_printf("NE2000: ne2000_ether_recv() select failed\n");
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return -1;
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}
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if (!FD_ISSET(s->fdnet, &readset)) {
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N_printf("NE2000: ne2000_ether_recv() nothing to read\n");
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return -1;
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}
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ret = read(s->fdnet, buf, bufsiz);
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if (ret < 0) {
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N_printf("NE2000: ne2000_ether_recv() read failed\n");
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return -1;
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}
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N_printf("NE2000: ne2000_ether_recv() read %d bytes\n", ret);
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N_printhdr(buf);
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return ret;
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}
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static void ne2000_receive_req_async(void *arg)
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{
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NE2000State *s = &ne2000state;
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uint8_t mybuf[MAX_ETH_FRAME_SIZE];
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int ret;
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N_printf("NE2000: ne2000_receive_req_async() called\n");
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ret = ne2000_ether_recv(s, mybuf, sizeof mybuf);
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if (ret < 0)
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return;
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ne2000_receive(s, mybuf, ret);
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}
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static void ne2000_update_irq(NE2000State *s)
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{
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int isr;
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isr = (s->isr & s->imr) & 0x7f;
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#if defined(DEBUG_NE2000)
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N_printf("NE2000: Set IRQ to %d (%02x %02x)\n", isr ? 1 : 0, s->isr, s->imr);
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#endif
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ne2000_irq_activate(isr != 0);
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}
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static int ne2000_buffer_full(NE2000State *s)
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{
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int avail, index, boundary;
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N_printf("NE2000: ne2000_buffer_full()\n");
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index;
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else
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avail = (s->stop - s->start) - (index - boundary);
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if (avail < (MAX_ETH_FRAME_SIZE + 4))
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return 1;
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return 0;
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}
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#define MIN_BUF_SIZE 60
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static size_t ne2000_receive(NE2000State *s, const uint8_t *buf, size_t size_)
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{
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size_t size = size_;
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uint8_t *p;
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unsigned int total_len, next, avail, len, index;
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uint8_t buf1[MIN_BUF_SIZE];
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static const uint8_t broadcast_macaddr[6] =
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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N_printf("NE2000: ne2000_receive()\n");
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#if defined(DEBUG_NE2000)
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N_printf("NE2000: received len=%zd\n", size);
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#endif
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if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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return -1;
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/* XXX: check this */
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if (s->rxcr & 0x10) {
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/* promiscuous: receive all */
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} else {
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if (!memcmp(buf, broadcast_macaddr, 6)) {
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/* broadcast address */
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if (!(s->rxcr & 0x04))
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return size;
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} else if (buf[0] & 0x01) {
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/* multicast */
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if (!(s->rxcr & 0x08))
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return size;
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#if 0
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mcast_idx = compute_mcast_idx(buf);
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if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
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return size;
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#else
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return size;
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#endif
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} else if (s->mem[0] == buf[0] &&
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s->mem[2] == buf[1] &&
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s->mem[4] == buf[2] &&
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s->mem[6] == buf[3] &&
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s->mem[8] == buf[4] &&
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s->mem[10] == buf[5]) {
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/* match */
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} else {
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return size;
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}
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}
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size);
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1;
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size = MIN_BUF_SIZE;
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}
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index = s->curpag << 8;
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff);
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if (next >= s->stop)
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next -= (s->stop - s->start);
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/* prepare packet header */
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p = s->mem + index;
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s->rsr = ENRSR_RXOK; /* receive status */
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/* XXX: check this */
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if (buf[0] & 0x01)
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s->rsr |= ENRSR_PHY;
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p[0] = s->rsr;
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p[1] = next >> 8;
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p[2] = total_len;
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p[3] = total_len >> 8;
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index += 4;
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/* write packet data */
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while (size > 0) {
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if (index <= s->stop)
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avail = s->stop - index;
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|
else
|
|
avail = 0;
|
|
len = size;
|
|
if (len > avail)
|
|
len = avail;
|
|
memcpy(s->mem + index, buf, len);
|
|
buf += len;
|
|
index += len;
|
|
if (index == s->stop)
|
|
index = s->start;
|
|
size -= len;
|
|
}
|
|
s->curpag = next >> 8;
|
|
|
|
/* now we can signal we have received something */
|
|
s->isr |= ENISR_RX;
|
|
ne2000_update_irq(s);
|
|
|
|
return size_;
|
|
}
|
|
|
|
static void ne2000_ioport_write(NE2000State *s, uint32_t addr, uint32_t val)
|
|
{
|
|
int offset, page, index;
|
|
|
|
N_printf("NE2000: ne2000_ioport_write()\n");
|
|
|
|
addr &= 0xf;
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
|
#endif
|
|
if (addr == E8390_CMD) {
|
|
/* control register */
|
|
s->cmd = val;
|
|
if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
|
|
s->isr &= ~ENISR_RESET;
|
|
/* test specific case: zero length transfer */
|
|
if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
|
s->rcnt == 0) {
|
|
s->isr |= ENISR_RDC;
|
|
ne2000_update_irq(s);
|
|
}
|
|
if (val & E8390_TRANS) {
|
|
index = (s->tpsr << 8);
|
|
/* XXX: next 2 lines are a hack to make netware 3.11 work */
|
|
if (index >= NE2000_PMEM_END)
|
|
index -= NE2000_PMEM_SIZE;
|
|
/* fail safe: check range on the transmitted length */
|
|
if (index + s->tcnt <= NE2000_PMEM_END) {
|
|
ne2000_ether_send(s, s->mem + index, s->tcnt);
|
|
}
|
|
/* signal end of transfer */
|
|
s->tsr = ENTSR_PTX;
|
|
s->isr |= ENISR_TX;
|
|
s->cmd &= ~E8390_TRANS;
|
|
ne2000_update_irq(s);
|
|
}
|
|
}
|
|
} else {
|
|
page = s->cmd >> 6;
|
|
offset = addr | (page << 4);
|
|
switch(offset) {
|
|
case EN0_STARTPG:
|
|
s->start = val << 8;
|
|
break;
|
|
case EN0_STOPPG:
|
|
s->stop = val << 8;
|
|
break;
|
|
case EN0_BOUNDARY:
|
|
s->boundary = val;
|
|
break;
|
|
case EN0_IMR:
|
|
s->imr = val;
|
|
ne2000_update_irq(s);
|
|
break;
|
|
case EN0_TPSR:
|
|
s->tpsr = val;
|
|
break;
|
|
case EN0_TCNTLO:
|
|
s->tcnt = (s->tcnt & 0xff00) | val;
|
|
break;
|
|
case EN0_TCNTHI:
|
|
s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
|
|
break;
|
|
case EN0_RSARLO:
|
|
s->rsar = (s->rsar & 0xff00) | val;
|
|
break;
|
|
case EN0_RSARHI:
|
|
s->rsar = (s->rsar & 0x00ff) | (val << 8);
|
|
break;
|
|
case EN0_RCNTLO:
|
|
s->rcnt = (s->rcnt & 0xff00) | val;
|
|
break;
|
|
case EN0_RCNTHI:
|
|
s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
|
|
break;
|
|
case EN0_RXCR:
|
|
s->rxcr = val;
|
|
break;
|
|
case EN0_DCFG:
|
|
s->dcfg = val;
|
|
break;
|
|
case EN0_ISR:
|
|
s->isr &= ~(val & 0x7f);
|
|
ne2000_update_irq(s);
|
|
break;
|
|
case EN1_PHYS ... EN1_PHYS + 5:
|
|
s->phys[offset - EN1_PHYS] = val;
|
|
break;
|
|
case EN1_CURPAG:
|
|
s->curpag = val;
|
|
break;
|
|
case EN1_MULT ... EN1_MULT + 7:
|
|
s->mult[offset - EN1_MULT] = val;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static uint32_t ne2000_ioport_read(NE2000State *s, uint32_t addr)
|
|
{
|
|
int offset, page, ret;
|
|
|
|
N_printf("NE2000: ne2000_ioport_read()\n");
|
|
|
|
addr &= 0xf;
|
|
if (addr == E8390_CMD) {
|
|
ret = s->cmd;
|
|
} else {
|
|
page = s->cmd >> 6;
|
|
offset = addr | (page << 4);
|
|
switch(offset) {
|
|
case EN0_TSR:
|
|
ret = s->tsr;
|
|
break;
|
|
case EN0_BOUNDARY:
|
|
ret = s->boundary;
|
|
break;
|
|
case EN0_ISR:
|
|
ret = s->isr;
|
|
break;
|
|
case EN0_RSARLO:
|
|
ret = s->rsar & 0x00ff;
|
|
break;
|
|
case EN0_RSARHI:
|
|
ret = s->rsar >> 8;
|
|
break;
|
|
case EN1_PHYS ... EN1_PHYS + 5:
|
|
ret = s->phys[offset - EN1_PHYS];
|
|
break;
|
|
case EN1_CURPAG:
|
|
ret = s->curpag;
|
|
break;
|
|
case EN1_MULT ... EN1_MULT + 7:
|
|
ret = s->mult[offset - EN1_MULT];
|
|
break;
|
|
case EN0_RSR:
|
|
ret = s->rsr;
|
|
break;
|
|
case EN2_STARTPG:
|
|
ret = s->start >> 8;
|
|
break;
|
|
case EN2_STOPPG:
|
|
ret = s->stop >> 8;
|
|
break;
|
|
case EN0_RTL8029ID0:
|
|
ret = 0x50;
|
|
break;
|
|
case EN0_RTL8029ID1:
|
|
ret = 0x43;
|
|
break;
|
|
case EN3_CONFIG0:
|
|
ret = 0; /* 10baseT media */
|
|
break;
|
|
case EN3_CONFIG2:
|
|
ret = 0x40; /* 10baseT active */
|
|
break;
|
|
case EN3_CONFIG3:
|
|
ret = 0x40; /* Full duplex */
|
|
break;
|
|
default:
|
|
ret = 0x00;
|
|
break;
|
|
}
|
|
}
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
|
|
uint32_t val)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_writeb()\n");
|
|
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
s->mem[addr] = val;
|
|
}
|
|
}
|
|
|
|
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
|
|
uint32_t val)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_writew()\n");
|
|
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
*(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
|
|
}
|
|
}
|
|
|
|
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
|
|
uint32_t val)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_writel()\n");
|
|
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_readb()\n");
|
|
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
return s->mem[addr];
|
|
} else {
|
|
return 0xff;
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_readw()\n");
|
|
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
|
} else {
|
|
return 0xffff;
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
|
|
{
|
|
N_printf("NE2000: ne2000_mem_readl()\n");
|
|
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
|
} else {
|
|
return 0xffffffff;
|
|
}
|
|
}
|
|
|
|
static inline void ne2000_dma_update(NE2000State *s, int len)
|
|
{
|
|
N_printf("NE2000: ne2000_dma_update()\n");
|
|
|
|
s->rsar += len;
|
|
/* wrap */
|
|
/* XXX: check what to do if rsar > stop */
|
|
if (s->rsar == s->stop)
|
|
s->rsar = s->start;
|
|
|
|
if (s->rcnt <= len) {
|
|
s->rcnt = 0;
|
|
/* signal end of transfer */
|
|
s->isr |= ENISR_RDC;
|
|
ne2000_update_irq(s);
|
|
} else {
|
|
s->rcnt -= len;
|
|
}
|
|
}
|
|
|
|
static void ne2000_asic_ioport_write(NE2000State *s, uint32_t addr, uint32_t val)
|
|
{
|
|
N_printf("NE2000: ne2000_asic_ioport_write()\n");
|
|
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: asic write val=0x%04x\n", val);
|
|
#endif
|
|
if (s->rcnt == 0)
|
|
return;
|
|
if (s->dcfg & 0x01) {
|
|
/* 16 bit access */
|
|
ne2000_mem_writew(s, s->rsar, val);
|
|
ne2000_dma_update(s, 2);
|
|
} else {
|
|
/* 8 bit access */
|
|
ne2000_mem_writeb(s, s->rsar, val);
|
|
ne2000_dma_update(s, 1);
|
|
}
|
|
}
|
|
|
|
static uint32_t ne2000_asic_ioport_read(NE2000State *s, uint32_t addr)
|
|
{
|
|
int ret;
|
|
|
|
N_printf("NE2000: ne2000_asic_ioport_read()\n");
|
|
|
|
if (s->dcfg & 0x01) {
|
|
/* 16 bit access */
|
|
ret = ne2000_mem_readw(s, s->rsar);
|
|
ne2000_dma_update(s, 2);
|
|
} else {
|
|
/* 8 bit access */
|
|
ret = ne2000_mem_readb(s, s->rsar);
|
|
ne2000_dma_update(s, 1);
|
|
}
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: asic read val=0x%04x\n", ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static void ne2000_asic_ioport_writel(NE2000State *s, uint32_t addr, uint32_t val)
|
|
{
|
|
N_printf("NE2000: ne2000_asic_ioport_writel()\n");
|
|
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: asic writel val=0x%04x\n", val);
|
|
#endif
|
|
if (s->rcnt == 0)
|
|
return;
|
|
/* 32 bit access */
|
|
ne2000_mem_writel(s, s->rsar, val);
|
|
ne2000_dma_update(s, 4);
|
|
}
|
|
|
|
static uint32_t ne2000_asic_ioport_readl(NE2000State *s, uint32_t addr)
|
|
{
|
|
int ret;
|
|
|
|
N_printf("NE2000: ne2000_asic_ioport_readl()\n");
|
|
|
|
/* 32 bit access */
|
|
ret = ne2000_mem_readl(s, s->rsar);
|
|
ne2000_dma_update(s, 4);
|
|
#ifdef DEBUG_NE2000
|
|
N_printf("NE2000: asic readl val=0x%04x\n", ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static void ne2000_reset_ioport_write(NE2000State *s, uint32_t addr, uint32_t val)
|
|
{
|
|
/* nothing to do (end of reset pulse) */
|
|
N_printf("NE2000: ne2000_reset_ioport_write()\n");
|
|
}
|
|
|
|
static uint32_t ne2000_reset_ioport_read(NE2000State *s, uint32_t addr)
|
|
{
|
|
N_printf("NE2000: ne2000_reset_ioport_read()\n");
|
|
|
|
_ne2000_reset(s);
|
|
return 0;
|
|
}
|
|
|
|
static uint64_t ne2000_read(NE2000State *s, uint32_t addr, unsigned size)
|
|
{
|
|
N_printf("NE2000: ne2000_read()\n");
|
|
|
|
if (addr < 0x10 && size == 1) {
|
|
return ne2000_ioport_read(s, addr);
|
|
} else if (addr == 0x10) {
|
|
if (size <= 2) {
|
|
return ne2000_asic_ioport_read(s, addr);
|
|
} else {
|
|
return ne2000_asic_ioport_readl(s, addr);
|
|
}
|
|
} else if (addr == 0x1f && size == 1) {
|
|
return ne2000_reset_ioport_read(s, addr);
|
|
}
|
|
return ((uint64_t)1 << (size * 8)) - 1;
|
|
}
|
|
|
|
static void ne2000_write(NE2000State *s, uint32_t addr, uint64_t data, unsigned size)
|
|
{
|
|
N_printf("NE2000: ne2000_write()\n");
|
|
|
|
if (addr < 0x10 && size == 1) {
|
|
ne2000_ioport_write(s, addr, data);
|
|
} else if (addr == 0x10) {
|
|
if (size <= 2) {
|
|
ne2000_asic_ioport_write(s, addr, data);
|
|
} else {
|
|
ne2000_asic_ioport_writel(s, addr, data);
|
|
}
|
|
} else if (addr == 0x1f && size == 1) {
|
|
ne2000_reset_ioport_write(s, addr, data);
|
|
}
|
|
}
|
|
|
|
/* from Scott Pitcher's driver */
|
|
|
|
/* --------------------------------- */
|
|
/* 16 bit io functions - only on data port */
|
|
|
|
Bit16u ne2000_io_read16(ioport_t port)
|
|
{
|
|
NE2000State *s = &ne2000state;
|
|
ioport_t addr = port - NE2000_IOBASE;
|
|
|
|
N_printf("\nNE2000: ne2000_io_read16()\n");
|
|
|
|
if (addr == 0x10)
|
|
return ne2000_read(s, addr, 2);
|
|
else
|
|
return ne2000_read(s, addr, 1);
|
|
}
|
|
|
|
void ne2000_io_write16(ioport_t port, Bit16u value)
|
|
{
|
|
NE2000State *s = &ne2000state;
|
|
ioport_t addr = port - NE2000_IOBASE;
|
|
|
|
N_printf("\nNE2000: ne2000_io_write16()\n");
|
|
|
|
if (addr == 0x10)
|
|
ne2000_write(s, addr, value, 2);
|
|
else
|
|
ne2000_write(s, addr, (uint8_t)value, 1); /* default to 8 bit */
|
|
}
|
|
|
|
/* --------------------------------- */
|
|
|
|
/* handle io reads from ne2000 */
|
|
|
|
Bit8u ne2000_io_read8(ioport_t port)
|
|
{
|
|
NE2000State *s = &ne2000state;
|
|
ioport_t addr = port - NE2000_IOBASE;
|
|
|
|
N_printf("\nNE2000: ne2000_io_read8() %d\n", addr);
|
|
return ne2000_read(s, addr, 1);
|
|
}
|
|
|
|
/* --------------------------------- */
|
|
|
|
/* handle io writes to ne2000 */
|
|
|
|
void ne2000_io_write8(ioport_t port, Bit8u value)
|
|
{
|
|
NE2000State *s = &ne2000state;
|
|
ioport_t addr = port - NE2000_IOBASE;
|
|
|
|
N_printf("\nNE2000: ne2000_io_write8() %d, 0x%02x\n", addr, value);
|
|
ne2000_write(s, addr, value, 1);
|
|
}
|
|
|
|
/* activate our irq */
|
|
static void ne2000_irq_activate(int level)
|
|
{
|
|
NE2000State *s = &ne2000state;
|
|
|
|
N_printf("NE2000: ne2000_irq_activate(%d)\n", level);
|
|
|
|
if (level)
|
|
pic_request(s->irq);
|
|
else
|
|
pic_untrigger(s->irq);
|
|
}
|
|
|
|
/* debug print an ethernet header */
|
|
#ifdef DEBUG_NE2000
|
|
static void N_printhdr(uint8_t *buf)
|
|
{
|
|
N_printf("NE2000: dest[%02x,%02x,%02x,%02x,%02x,%02x]\n"
|
|
" src[%02x,%02x,%02x,%02x,%02x,%02x]\n"
|
|
" prot[%02x,%02x]\n",
|
|
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
|
|
buf[6], buf[7], buf[8], buf[9], buf[10], buf[11],
|
|
buf[12], buf[13]);
|
|
}
|
|
#endif
|