83 lines
2.4 KiB
Diff
83 lines
2.4 KiB
Diff
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From ea0b70265614b950d1e2ed48a9581ecd5e63ac97 Mon Sep 17 00:00:00 2001
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From: Ulrich Hecht <uli@suse.de>
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Date: Fri, 24 Jul 2009 17:25:37 +0200
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Subject: [PATCH 20/33] TCG "sync" op (32-bit targets fixed)
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sync allows concurrent accesses to locations in memory through different TCG
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variables. This comes in handy when you are emulating CPU registers that can
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be used as either 32 or 64 bit, as TCG doesn't know anything about aliases.
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See the s390x target for an example.
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Fixed to not break 32-bit target builds.
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Signed-off-by: Ulrich Hecht <uli@suse.de>
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---
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tcg/tcg-op.h | 12 ++++++++++++
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tcg/tcg-opc.h | 2 ++
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tcg/tcg.c | 6 ++++++
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3 files changed, 20 insertions(+), 0 deletions(-)
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diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
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index 7cb6934..cfd6160 100644
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--- a/tcg/tcg-op.h
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+++ b/tcg/tcg-op.h
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@@ -316,6 +316,18 @@ static inline void tcg_gen_br(int label)
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tcg_gen_op1i(INDEX_op_br, label);
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}
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+static inline void tcg_gen_sync_i32(TCGv_i32 arg)
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+{
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+ tcg_gen_op1_i32(INDEX_op_sync_i32, arg);
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+}
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+
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+#if TCG_TARGET_REG_BITS == 64
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+static inline void tcg_gen_sync_i64(TCGv_i64 arg)
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+{
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+ tcg_gen_op1_i64(INDEX_op_sync_i64, arg);
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+}
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+#endif
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+
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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if (!TCGV_EQUAL_I32(ret, arg))
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diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
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index 3a095fc..654a45f 100644
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--- a/tcg/tcg-opc.h
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+++ b/tcg/tcg-opc.h
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@@ -40,6 +40,7 @@ DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
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DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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+DEF2(sync_i32, 0, 1, 0, 0)
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DEF2(mov_i32, 1, 1, 0, 0)
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DEF2(movi_i32, 1, 0, 1, 0)
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/* load/store */
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@@ -103,6 +104,7 @@ DEF2(neg_i32, 1, 1, 0, 0)
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#endif
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#if TCG_TARGET_REG_BITS == 64
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+DEF2(sync_i64, 0, 1, 0, 0)
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DEF2(mov_i64, 1, 1, 0, 0)
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DEF2(movi_i64, 1, 0, 1, 0)
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/* load/store */
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diff --git a/tcg/tcg.c b/tcg/tcg.c
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index 299bff6..86e16fa 100644
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--- a/tcg/tcg.c
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+++ b/tcg/tcg.c
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@@ -1927,6 +1927,12 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
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// dump_regs(s);
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#endif
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switch(opc) {
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+ case INDEX_op_sync_i32:
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+#if TCG_TARGET_REG_BITS == 64
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+ case INDEX_op_sync_i64:
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+#endif
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+ temp_save(s, args[0], s->reserved_regs);
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+ break;
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case INDEX_op_mov_i32:
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#if TCG_TARGET_REG_BITS == 64
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case INDEX_op_mov_i64:
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--
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1.6.2.1
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