342 lines
10 KiB
Diff
342 lines
10 KiB
Diff
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#qemu-only -> submit upstream qemu
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Index: kvm-75/qemu/Makefile.target
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===================================================================
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--- kvm-75.orig/qemu/Makefile.target
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+++ kvm-75/qemu/Makefile.target
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@@ -610,7 +610,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
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OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o
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OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
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OBJS+= cirrus_vga.o apic.o parallel.o acpi.o piix_pci.o
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-OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o extboot.o
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+OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o extboot.o hpet.o
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ifeq ($(USE_KVM_PIT), 1)
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OBJS+= i8254-kvm.o
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endif
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Index: kvm-75/qemu/hw/hpet.c
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===================================================================
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--- /dev/null
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+++ kvm-75/qemu/hw/hpet.c
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@@ -0,0 +1,322 @@
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+/*
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+ * High Precisition Event Timer emulation
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+ *
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+ * Copyright (c) 2007 Alexander Graf
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+ *
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+ * This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU Lesser General Public
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+ * License as published by the Free Software Foundation; either
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+ * version 2 of the License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * Lesser General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU Lesser General Public
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+ * License along with this library; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ *
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+ * *****************************************************************
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+ *
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+ * This driver attempts to emulate an HPET device in software. It is by no
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+ * means complete and is prone to break on certain conditions.
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+ *
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+ */
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+#include "hw.h"
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+#include "console.h"
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+#include "qemu-timer.h"
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+
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+#define HPET_DEBUG
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+
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+#define HPET_BASE 0xfed00000
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+
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+#define HPET_NUM_TIMERS 3
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+#define HPET_TIMER_TYPE_LEVEL 1
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+#define HPET_TIMER_TYPE_EDGE 0
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+#define HPET_TIMER_DELIVERY_APIC 0
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+#define HPET_TIMER_DELIVERY_FSB 1
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+#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
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+#define HPET_TIMER_CAP_PER_INT (1 << 4)
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+
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+struct HPETState;
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+typedef struct HPETTimer {
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+ QEMUTimer *timer;
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+ struct HPETState *state;
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+ uint8_t type;
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+ uint8_t active;
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+ uint8_t delivery;
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+ uint8_t apic_port;
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+ uint8_t periodic;
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+ uint8_t enabled;
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+ uint32_t comparator; // if(hpet_counter == comparator) IRQ();
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+ qemu_irq irq;
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+} HPETTimer;
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+
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+typedef struct HPETState {
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+ uint64_t hpet_counter;
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+ int64_t next_periodic_time;
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+ uint8_t active;
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+ qemu_irq *irqs;
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+ HPETTimer timer[HPET_NUM_TIMERS];
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+} HPETState;
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+
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+static void update_irq(struct HPETTimer *timer)
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+{
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+ qemu_set_irq(timer->irq, timer->active && timer->state->active);
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+}
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+
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+static void update_irq_all(struct HPETState *s)
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+{
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+ int i;
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+ for(i=0; i<HPET_NUM_TIMERS; i++)
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+ update_irq(&s->timer[i]);
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+}
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+
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+static void hpet_timer(void *opaque)
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+{
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+ HPETTimer *s = (HPETTimer*)opaque;
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+ printf("hpet i!\n");
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+ if(s->periodic) {
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+ printf("periodic hpet!\n");
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+ qemu_mod_timer(s->timer, qemu_get_clock(vm_clock) + ((s->comparator) * (ticks_per_sec * 99) / 100));
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+ }
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+ s->active = 1;
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+ update_irq(s);
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+}
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+
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+static void hpet_check(HPETTimer *s)
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+{
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+ if(s->enabled) {
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+ if(s->periodic)
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+ qemu_mod_timer(s->timer, qemu_get_clock(vm_clock) + s->comparator * (ticks_per_sec * 99) / 100);
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+ else
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+ qemu_mod_timer(s->timer, qemu_get_clock(vm_clock) + ((s->comparator - s->state->hpet_counter) * (ticks_per_sec * 99) / 100));
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+ }
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+}
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+
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+static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
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+{
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+#ifdef HPET_DEBUG
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+ printf("qemu: hpet_read b at %#lx\n", addr);
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+#endif
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+ return 10;
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+}
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+
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+static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
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+{
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+#ifdef HPET_DEBUG
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+ printf("qemu: hpet_read w at %#lx\n", addr);
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+#endif
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+ return 10;
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+}
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+
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+static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
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+{
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+ HPETState *s = (HPETState *)opaque;
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+#ifdef HPET_DEBUG
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+ printf("qemu: hpet_read l at %#lx\n", addr);
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+#endif
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+ switch(addr - HPET_BASE) {
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+ case 0x00:
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+ return 0x8086a201;
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+ case 0x04:
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+ return 0x0429b17f;
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+ case 0x10:
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+ case 0x14:
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+ return 0;
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+ case 0xf0:
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+ return s->hpet_counter;
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+ case 0xf4:
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+ return 0;
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+ case 0x20:
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+ {
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+ uint32_t retval = 0;
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+ int i;
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+ for(i=0; i<HPET_NUM_TIMERS; i++) {
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+ if(s->timer[i].type == HPET_TIMER_TYPE_LEVEL)
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+ retval |= s->timer[i].active << i;
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+ }
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+ return retval;
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+ }
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+ case 0x100 ... 0x3ff:
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+ {
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+ uint8_t timer_id = (addr - HPET_BASE - 0x100) / 0x20;
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+ HPETTimer *timer = &s->timer[timer_id];
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+
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+ switch((addr - HPET_BASE - 0x100) % 0x20) {
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+ case 0x0:
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+ return ((timer->delivery == HPET_TIMER_DELIVERY_FSB) << 14)
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+ | (timer->apic_port << 9)
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+ | HPET_TIMER_CAP_PER_INT
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+ | (timer->periodic << 3)
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+ | (timer->enabled << 2)
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+ | (timer->type << 1);
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+ case 0x4: // Interrupt capabilities
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+ return 0x00ff;
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+ case 0x8: // comparator register
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+ return timer->comparator;
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+ case 0xc:
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+ return 0x0;
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+ }
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+ }
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+ break;
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+ }
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+
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+#ifdef HPET_DEBUG
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+ printf("qemu: invalid hpet_read l at %#x\n", addr);
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+#endif
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+ return 10;
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+}
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+
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+static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
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+ uint32_t value)
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+{
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+#ifdef HPET_DEBUG
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+ printf("qemu: invalid hpet_write b at %#x = %#x\n", addr, value);
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+#endif
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+}
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+
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+static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
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+ uint32_t value)
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+{
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+#ifdef HPET_DEBUG
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+ printf("qemu: invalid hpet_write w at %#x = %#x\n", addr, value);
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+#endif
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+}
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+
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+static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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+ uint32_t value)
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+{
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+ HPETState *s = (HPETState *)opaque;
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+#ifdef HPET_DEBUG
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+ printf("qemu: hpet_write l at %#x = %#x\n", addr, value);
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+#endif
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+ switch(addr - HPET_BASE) {
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+ case 0x00:
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+ return;
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+ case 0x10:
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+ case 0x14: // set interrupt enabled flag
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+ if(value < 2) {
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+ s->active = value;
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+ update_irq_all(s);
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+ } else {
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+#ifdef HPET_DEBUG
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+ printf("qemu: invalid hpet_write l at %#x = %#x\n", addr, value);
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+#endif
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+ }
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+ break;
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+ case 0x20:
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+ {
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+ int i;
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+ for(i=0; i<HPET_NUM_TIMERS; i++) {
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+ if(s->timer[i].type == HPET_TIMER_TYPE_LEVEL) {
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+ if(value & (1 << i)) {
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+ s->timer[i].active = 0;
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+ update_irq(&s->timer[i]);
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+ }
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+ }
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+ }
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+ }
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+ break;
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+ case 0xf0:
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+ s->hpet_counter = (s->hpet_counter & (0xffffffffULL << 32)) | value;
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+#ifdef HPET_DEBUG
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+ printf("qemu: HPET counter 0xf0 set to %#x -> %#llx\n", value, s->hpet_counter);
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+#endif
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+ break;
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+ case 0xf4:
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+ s->hpet_counter = (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
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+#ifdef HPET_DEBUG
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+ printf("qemu: HPET counter 0xf4 set to %#x -> %#llx\n", value, s->hpet_counter);
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+#endif
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+ break;
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+ case 0x100 ... 0x3ff:
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+ {
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+ uint8_t timer_id = (addr - HPET_BASE - 0x100) / 0x20;
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+ HPETTimer *timer = &s->timer[timer_id];
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+
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+ switch((addr - HPET_BASE - 0x100) % 0x20) {
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+ case 0x0:
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+ if(value & 1) break; // reserved
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+ timer->delivery = (value >> 14) & 1;
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+ timer->apic_port = (value >> 9) & 16;
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+ timer->irq = s->irqs[timer->apic_port];
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+ timer->periodic = (value >> 3) & 1;
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+ timer->enabled = (value >> 2) & 1;
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+ timer->type = (value >> 1) & 1;
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+#ifdef HPET_DEBUG
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+ printf("qemu: hpet_write l at %#x = %#x\n", addr, value);
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+#endif
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+ hpet_check(timer);
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+ break;
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+#ifdef HPET_DEBUG
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+ case 0x4: // Interrupt capabilities
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+ printf("qemu: invalid hpet_write l at %#x = %#x\n", addr, value);
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+ break;
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+#endif
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+ case 0x8: // comparator register
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+ timer->comparator = value;
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+ hpet_check(timer);
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+ break;
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+ case 0xc:
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+#ifdef HPET_DEBUG
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+ printf("qemu: invalid hpet_write l at %#x = %#x\n", addr, value);
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+#endif
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+ break;
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+ }
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+ }
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+ default:
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+ printf("qemu: invalid hpet_write l at %#x = %#x\n", addr, value);
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+ }
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+
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+}
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+
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+static CPUReadMemoryFunc *hpet_ram_read[] = {
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+ hpet_ram_readb,
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+ hpet_ram_readw,
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+ hpet_ram_readl,
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+};
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+
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+static CPUWriteMemoryFunc *hpet_ram_write[] = {
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+ hpet_ram_writeb,
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+ hpet_ram_writew,
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+ hpet_ram_writel,
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+};
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+
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+
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+void hpet_init(qemu_irq *irq) {
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+ int iomemtype, i;
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+ HPETState *s;
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+
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+ /* XXX this is a dirty hack for HPET support w/o LPC
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+ Actually this is a config descriptor for the RCBA */
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+ s = qemu_mallocz(sizeof(HPETState));
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+ s->irqs = irq;
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+
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+ for(i=0; i<HPET_NUM_TIMERS; i++) {
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+ HPETTimer *timer = &s->timer[i];
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+ timer->comparator = 0xffffffff;
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+ timer->state = s;
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+ timer->timer = qemu_new_timer(vm_clock, hpet_timer, s->timer+i);
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+ switch(i) {
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+ case 0:
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+ timer->apic_port = 2;
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+ break;
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+ case 1:
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+ timer->apic_port = 8;
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+ break;
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+ default:
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+ timer->apic_port = 0;
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+ break;
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+ }
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+ s->timer[i].irq = irq[timer->apic_port];
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+ }
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+
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+ /* HPET Area */
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+
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+ iomemtype = cpu_register_io_memory(0, hpet_ram_read,
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+ hpet_ram_write, s);
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+
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+ cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
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+}
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