359 lines
9.6 KiB
Diff
359 lines
9.6 KiB
Diff
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2004-09-02 Steven Munroe <sjmunroe@us.ibm.com>
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[BZ #357]
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* stdlib/tst-setcontext.c (test_stack): Added test for stack clobber.
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(main): Call test_stack.
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* sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
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(__getcontext): Push stack frame then save parms in local frame.
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Improve instruction scheduling.
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* sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
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(__swapcontext): Push stack frame then save parms in local frame.
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Improve instruction scheduling.
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diff -urN libc23-cvstip-20040830/stdlib/tst-setcontext.c libc23/stdlib/tst-setcontext.c
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--- libc23-cvstip-20040830/stdlib/tst-setcontext.c 2002-08-30 22:21:40.000000000 -0500
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+++ libc23/stdlib/tst-setcontext.c 2004-09-02 10:10:28.055274880 -0500
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@@ -72,6 +72,55 @@
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was_in_f2 = 1;
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}
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+void
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+test_stack(volatile int a, volatile int b,
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+ volatile int c, volatile int d)
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+{
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+ volatile int e = 5;
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+ volatile int f = 6;
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+ ucontext_t uc;
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+
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+ /* Test for cases where getcontext is clobbering the callers
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+ stack, including parameters. */
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+ getcontext(&uc);
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+
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+ if (a != 1)
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+ {
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+ printf ("%s: getcontext clobbers parm a\n", __FUNCTION__);
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+ exit (1);
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+ }
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+
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+ if (b != 2)
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+ {
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+ printf ("%s: getcontext clobbers parm b\n", __FUNCTION__);
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+ exit (1);
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+ }
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+
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+ if (c != 3)
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+ {
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+ printf ("%s: getcontext clobbers parm c\n", __FUNCTION__);
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+ exit (1);
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+ }
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+
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+ if (d != 4)
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+ {
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+ printf ("%s: getcontext clobbers parm d\n", __FUNCTION__);
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+ exit (1);
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+ }
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+
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+ if (e != 5)
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+ {
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+ printf ("%s: getcontext clobbers varible e\n", __FUNCTION__);
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+ exit (1);
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+ }
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+
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+ if (f != 6)
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+ {
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+ printf ("%s: getcontext clobbers variable f\n", __FUNCTION__);
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+ exit (1);
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+ }
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+}
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+
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volatile int global;
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int
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@@ -88,6 +137,8 @@
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printf ("%s: getcontext: %m\n", __FUNCTION__);
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exit (1);
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}
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+
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+ test_stack (1, 2, 3, 4);
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/* Play some tricks with this context. */
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if (++global == 1)
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diff -urN libc23-cvstip-20040830/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S libc23/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S
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--- libc23-cvstip-20040830/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S 2004-06-15 15:02:20.000000000 -0500
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+++ libc23/sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext.S 2004-09-02 12:46:16.064221704 -0500
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@@ -27,18 +27,22 @@
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.machine "altivec"
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ENTRY(__getcontext)
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+ stwu r1,-16(r1)
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+/* Insure that the _UC_REGS start on a quadword boundary. */
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stw r3,_FRAME_PARM_SAVE1(r1)
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addi r3,r3,_UC_REG_SPACE+12
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clrrwi r3,r3,4
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+
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+/* Save the general purpose registers */
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stw r0,_UC_GREGS+(PT_R0*4)(r3)
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mflr r0
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- stw r1,_UC_GREGS+(PT_R1*4)(r3)
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- stwu r1,-16(r1)
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+ stw r2,_UC_GREGS+(PT_R2*4)(r3)
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+ stw r4,_UC_GREGS+(PT_R4*4)(r3)
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+/* Set the callers LR_SAVE, and the ucontext LR and NIP to the callers
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+ return address. */
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stw r0,_UC_GREGS+(PT_LNK*4)(r3)
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stw r0,_UC_GREGS+(PT_NIP*4)(r3)
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stw r0,_FRAME_LR_SAVE+16(r1)
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- stw r2,_UC_GREGS+(PT_R2*4)(r3)
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- stw r4,_UC_GREGS+(PT_R4*4)(r3)
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stw r5,_UC_GREGS+(PT_R5*4)(r3)
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stw r6,_UC_GREGS+(PT_R6*4)(r3)
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stw r7,_UC_GREGS+(PT_R7*4)(r3)
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@@ -66,23 +70,28 @@
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stw r29,_UC_GREGS+(PT_R29*4)(r3)
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stw r30,_UC_GREGS+(PT_R30*4)(r3)
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stw r31,_UC_GREGS+(PT_R31*4)(r3)
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- mfctr r0
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- stw r0,_UC_GREGS+(PT_CTR*4)(r3)
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- mfxer r0
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- stw r0,_UC_GREGS+(PT_XER*4)(r3)
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- mfcr r0
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- stw r0,_UC_GREGS+(PT_CCR*4)(r3)
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-
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- /* Set the return value of getcontext to "success". R3 is the only
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- register whose value is not preserved in the saved context. */
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+/* Save the value of R1. We had to push the stack before we
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+ had the address of uc_reg_space. So compute the address of
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+ the callers stack pointer and save it as R1. */
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+ addi r8,r1,16
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li r0,0
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+/* Save the count, exception and condition registers. */
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+ mfctr r11
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+ mfxer r10
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+ mfcr r9
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+ stw r8,_UC_GREGS+(PT_R1*4)(r3)
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+ stw r11,_UC_GREGS+(PT_CTR*4)(r3)
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+ stw r10,_UC_GREGS+(PT_XER*4)(r3)
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+ stw r9,_UC_GREGS+(PT_CCR*4)(r3)
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+/* Set the return value of getcontext to "success". R3 is the only
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+ register whose value is not preserved in the saved context. */
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stw r0,_UC_GREGS+(PT_R3*4)(r3)
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- /* Zero fill fields that can't be set in user state. */
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+/* Zero fill fields that can't be set in user state. */
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stw r0,_UC_GREGS+(PT_MSR*4)(r3)
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stw r0,_UC_GREGS+(PT_MQ*4)(r3)
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- /* Save the floating-point registers */
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+/* Save the floating-point registers */
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stfd fp0,_UC_FREGS+(0*8)(r3)
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stfd fp1,_UC_FREGS+(1*8)(r3)
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stfd fp2,_UC_FREGS+(2*8)(r3)
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@@ -136,21 +145,31 @@
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lwz r7,_dl_hwcap@l(r7)
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#endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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- beq L(no_vec)
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la r10,(_UC_VREGS)(r3)
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la r9,(_UC_VREGS+16)(r3)
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+
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+ beq L(no_vec)
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+/* address of the combined VSCR/VSAVE quadword. */
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+ la r8,(_UC_VREGS+512)(r3)
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+/* Save the vector registers */
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stvx v0,0,r10
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stvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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+/* We need to get the Vector Status and Control Register early to avoid
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+ store order problems later with the VSAVE register that shares the
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+ same quadword. */
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+ mfvscr v0
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stvx v2,0,r10
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stvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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+ stvx v0,0,r8
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+
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stvx v4,0,r10
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stvx v5,0,r9
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addi r10,r10,32
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@@ -216,20 +235,18 @@
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addi r10,r10,32
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addi r9,r9,32
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+ mfspr r0,VRSAVE
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stvx v30,0,r10
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stvx v31,0,r9
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- addi r10,r10,32
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- addi r9,r9,32
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- mfvscr v0
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- mfspr r0,VRSAVE
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- stvx v0,0,r10
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- sync
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- stw r0,0(r10)
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+ stw r0,0(r8)
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L(no_vec):
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-/* Restore ucontext (parm1) from stack. */
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- lwz r12,_FRAME_PARM_SAVE1+16(r1)
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+/* We need to set up parms and call sigprocmask which will clobber
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+ volatile registers. So before the call we need to retrieve the
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+ original ucontext ptr (parm1) from stack and store the UC_REGS_PTR
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+ (current R3). */
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+ lwz r12,_FRAME_PARM_SAVE1(r1)
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li r4,0
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stw r3,_UC_REGS_PTR(r12)
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addi r5,r12,_UC_SIGMASK
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diff -urN libc23-cvstip-20040830/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S libc23/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
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--- libc23-cvstip-20040830/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S 2004-06-15 15:02:20.000000000 -0500
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+++ libc23/sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S 2004-09-02 12:45:43.125302872 -0500
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@@ -27,22 +27,23 @@
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.machine "altivec"
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ENTRY(__swapcontext)
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- /* Save the current context */
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+ stwu r1,-16(r1)
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+/* Insure that the _UC_REGS start on a quadword boundary. */
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stw r3,_FRAME_PARM_SAVE1(r1)
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addi r3,r3,_UC_REG_SPACE+12
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+ stw r4,_FRAME_PARM_SAVE2(r1) /* new context pointer */
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clrrwi r3,r3,4
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+
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+/* Save the general purpose registers */
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stw r0,_UC_GREGS+(PT_R0*4)(r3)
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- stw r1,_UC_GREGS+(PT_R1*4)(r3)
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mflr r0
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- stwu r1,-16(r1)
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- stw r0,20(r1)
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- stw r31,12(r1)
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- stw r31,_UC_GREGS+(PT_R31*4)(r3)
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- mr r31,r4 /* new context pointer */
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+ stw r2,_UC_GREGS+(PT_R2*4)(r3)
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+ stw r4,_UC_GREGS+(PT_R4*4)(r3)
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+/* Set the callers LR_SAVE, and the ucontext LR and NIP to the callers
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+ return address. */
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stw r0,_UC_GREGS+(PT_LNK*4)(r3)
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stw r0,_UC_GREGS+(PT_NIP*4)(r3)
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- stw r2,_UC_GREGS+(PT_R2*4)(r3)
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- stw r4,_UC_GREGS+(PT_R4*4)(r3)
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+ stw r0,_FRAME_LR_SAVE+16(r1)
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stw r5,_UC_GREGS+(PT_R5*4)(r3)
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stw r6,_UC_GREGS+(PT_R6*4)(r3)
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stw r7,_UC_GREGS+(PT_R7*4)(r3)
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@@ -69,16 +70,23 @@
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stw r28,_UC_GREGS+(PT_R28*4)(r3)
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stw r29,_UC_GREGS+(PT_R29*4)(r3)
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stw r30,_UC_GREGS+(PT_R30*4)(r3)
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- mfctr r0
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- stw r0,_UC_GREGS+(PT_CTR*4)(r3)
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- mfxer r0
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- stw r0,_UC_GREGS+(PT_XER*4)(r3)
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- mfcr r0
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- stw r0,_UC_GREGS+(PT_CCR*4)(r3)
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-
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- /* Set the return value of swapcontext to "success". R3 is the only
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- register whose value is not preserved in the saved context. */
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+ stw r31,_UC_GREGS+(PT_R31*4)(r3)
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+
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+/* Save the value of R1. We had to push the stack before we
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+ had the address of uc_reg_space. So compute the address of
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+ the callers stack pointer and save it as R1. */
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+ addi r8,r1,16
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li r0,0
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+/* Save the count, exception and condition registers. */
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+ mfctr r11
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+ mfxer r10
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+ mfcr r9
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+ stw r8,_UC_GREGS+(PT_R1*4)(r3)
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+ stw r11,_UC_GREGS+(PT_CTR*4)(r3)
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+ stw r10,_UC_GREGS+(PT_XER*4)(r3)
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+ stw r9,_UC_GREGS+(PT_CCR*4)(r3)
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+/* Set the return value of getcontext to "success". R3 is the only
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+ register whose value is not preserved in the saved context. */
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stw r0,_UC_GREGS+(PT_R3*4)(r3)
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/* Zero fill fields that can't be set in user state. */
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@@ -138,20 +146,30 @@
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lwz r7,_dl_hwcap@l(r7)
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#endif
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andis. r7,r7,(PPC_FEATURE_HAS_ALTIVEC >> 16)
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- beq L(no_vec)
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la r10,(_UC_VREGS)(r3)
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la r9,(_UC_VREGS+16)(r3)
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+
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+ beq L(no_vec)
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+/* address of the combined VSCR/VSAVE quadword. */
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+ la r8,(_UC_VREGS+512)(r3)
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+/* Save the vector registers */
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stvx v0,0,r10
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stvx v1,0,r9
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addi r10,r10,32
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addi r9,r9,32
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+/* We need to get the Vector Status and Control Register early to avoid
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+ store order problems later with the VSAVE register that shares the
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+ same quadword. */
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+ mfvscr v0
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stvx v2,0,r10
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stvx v3,0,r9
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addi r10,r10,32
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addi r9,r9,32
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+
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+ stvx v0,0,r8
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stvx v4,0,r10
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stvx v5,0,r9
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@@ -218,20 +236,15 @@
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addi r10,r10,32
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addi r9,r9,32
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+ mfvscr v0
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stvx v30,0,r10
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stvx v31,0,r9
|
||
|
|
- addi r10,r10,32
|
||
|
|
- addi r9,r9,32
|
||
|
|
|
||
|
|
- mfvscr v0
|
||
|
|
- mfspr r0,VRSAVE
|
||
|
|
- stvx v0,0,r10
|
||
|
|
- sync
|
||
|
|
- stw r0,0(r10)
|
||
|
|
+ stw r0,0(r8)
|
||
|
|
|
||
|
|
L(no_vec):
|
||
|
|
/* Restore ucontext (parm1) from stack. */
|
||
|
|
- lwz r12,_FRAME_PARM_SAVE1+16(r1)
|
||
|
|
+ lwz r12,_FRAME_PARM_SAVE1(r1)
|
||
|
|
li r4,0
|
||
|
|
stw r3,_UC_REGS_PTR(r12)
|
||
|
|
addi r5,r12,_UC_SIGMASK
|
||
|
|
@@ -251,8 +264,8 @@
|
||
|
|
* r0, xer, ctr. We don't restore r2 since it will be used as
|
||
|
|
* the TLS pointer.
|
||
|
|
*/
|
||
|
|
- mr r4,r31
|
||
|
|
- lwz r31,_UC_REGS_PTR(r31)
|
||
|
|
+ lwz r4,_FRAME_PARM_SAVE2(r1)
|
||
|
|
+ lwz r31,_UC_REGS_PTR(r4)
|
||
|
|
lwz r0,_UC_GREGS+(PT_MSR*4)(r31)
|
||
|
|
cmpwi r0,0
|
||
|
|
bne L(do_sigret)
|
||
|
|
@@ -451,8 +464,7 @@
|
||
|
|
bctr
|
||
|
|
|
||
|
|
L(error_exit):
|
||
|
|
- lwz r31,12(r1)
|
||
|
|
- lwz r0,20(r1)
|
||
|
|
+ lwz r0,_FRAME_LR_SAVE+16(r1)
|
||
|
|
addi r1,r1,16
|
||
|
|
mtlr r0
|
||
|
|
blr
|